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IT6506 PROGRAMMING GUIDE

ITE Tech. INC.

-18-

2013/11/12

238

bInfo[7:0]

R/W

239

bInfo[15:0]

R/W

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Summary of Contents for IT6506

Page 1: ...IT6506 Programming Guide Ver 1 02 Tseng Jau Chih ITE Tech INC Last Update Date 2013 11 12 ...

Page 2: ...History ...

Page 3: ...eo Input Readback 9 Video Output Programming 10 Output RGB444 video 11 Output YCbCr444 video 11 Output YCbCr422 video sync seperated 11 Output YCbCr422 video sync embedded 12 Output YCbCr422 video sync embedded CCIR656 12 Color Converting 13 Enable Video Output 14 Chap 6 Audio Programming 15 Audio Input Information 15 Configure Audio Output 16 Audio Error 16 Chap 9 Registers 19 Bank 0 reg05 3 0 re...

Page 4: ...pliance with DisplayPort Specification V1 1a at 1 62 2 7 Gbps data rate Low bit rate High bit rate Support flexible 1 2 4 lanes configurations Full 10 8Gbps data rate support 4 lanes at 2 7Gbps Support DPCD Rev 1 1 Support HDCP 1 3 with HDCP key embedded Support Spread Spectrum Clocking up to 0 5 down spread to reduce EMI Support Source Connection Detection through AUX channel DC levels Support up...

Page 5: ...DD18 AGND AVCC DVSS18 QA33 QA34 36 QA29 SYSRSTN 11 12 13 14 97 98 OVSS QB10 QB11 QA16 QA17 QA18 QA19 95 OVDD 96 OVDD QB21 QB20 1 2 3 4 5 6 7 8 9 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 101 102 103 104 105 106 107 108 119 118 117 116 115 114 113 112 111 110 109 QB14 QB15 QB16 QB17 QB18 QB19 DDCSDA DDCSCL IVDD IVSS VSYNC HSYNC IVDD PCLK IVS...

Page 6: ...2 C and in bank 1 Reg1C0 access with I2 C slave address 0xB0 0xB2 sub address 0xC0 Reg2XX Where XX is a hexadecimal number to indicate the internal register accessed with subaddress XX of I2 C and in bank 2 The register 0x00 0x0F are common for all banks and the bank switching using as following bank 0 reg05 3 0 0 0 bank 1 reg05 3 0 0 1 bank 2 reg05 3 0 1 0 ...

Page 7: ...E 0xFE 0x1B3 0xFE 0x00 0x1B2 0xFF 4 0x1B2 0x05 1 0x1B5 0xFF 0x14 0x1B7 0xFF 0x33 0x1B8 0xFF 0x03 0x1CD 0xFF 0x80 0x1D2 0xFF 0x88 0x1D3 0xFF 0x69 0xEA 0x05 0x05 0xEA 0x05 0x04 0xEE 0x01 0x01 0x21 0xFF 0x0A 0x22 0xFF 0x64 0x2F 0xFF 0x7B 0xFD 0x05 4 0x31 0x40 0x40 0x32 0xFF 0xFF 0xB2 0x41 1 0xB7 0xFF 0x10 0xB8 0xFF 0x08 0xB9 0xFF 0x10 0xBA 0xFF 0x08 0xBB 0xFF 0x30 0xBC 0xFF 0x60 0xBD 0xF0 0x00 0xC0 0...

Page 8: ...PROGRAMMING GUIDE ITE Tech INC 5 2013 11 12 0xE6 0xFF 0x00 0xE9 0xFF 0x00 0xE5 0xFF 0x07 0xE7 0xFF 0xFF 0xE8 0xFF 0xFF 0xC9 0x09 0x09 0xED 0xC0 0x80 0xEE 0x02 0x00 0xEE 0xFC 0xFC 0xC9 0x10 0x10 0xF7 0x01 0x00 ...

Page 9: ...terrupt W1C RefAuxURCmd 1 AUX receive un support command interrupt W1C RefAuxSynErr 0 AUX receive sync length error interrupt W1C 09 LSNoSPDInfo 7 No SPD InfoFrame interrupt W1C LSNoMpegInfo 6 No Mpeg InfoFrame interrupt W1C LSNoAudInfo 5 No Audio InfoFrame interrupt W1C LSNoAVIInfo 4 No AVI InfoFrame interrupt W1C LSL3ECCInt 3 Lane 3 2 nibble error ECC interrupt W1C LSL2ECCInt 2 Lane 2 2 nibble e...

Page 10: ...NibbleErr 3 Lane 3 ECC 1 nibble error W1C LSL21NibbleErr 2 Lane 2 ECC 1 nibble error W1C LSL11NibbleErr 1 Lane 1 ECC 1 nibble error W1C LSL01NibbleErr 0 Lane 0 ECC 1 nibble error W1C Where interrupt mask is in RegE4 RegE9 and the bits are one to one mapping to reg07 reg0C Reg Name Bit Description Type Default Value E4 RegIntMask 7 0 7 0 Interrupt Mask 7 0 For register 07 one to one mapping R W 111...

Page 11: ...done status RO RegLnkTrnBusy 0 Link Training busy status RO The system state transition can refer these bits to judge the status transition IT6506 Capacity Configuring Set DP sink capability with the following table Feature Reg Setting Acceptable Maximum Lane Number 4 lanes reg22 2 0 100 2 lanes reg22 2 0 010 1 lane reg22 2 0 001 SSC reg22 6 1 for enabling Enhance Framing reg22 5 1 for enabling De...

Page 12: ... 0 Main stream attribute data H active width 7 0 RO 9C LSHWidth 15 8 7 0 Main stream attribute data H active width 15 8 RO 9D LSVTotal 7 0 7 0 Main stream attribute data V total 7 0 RO 9E LSVTotal 15 8 7 0 Main stream attribute data V total 15 8 RO 9F LSVStart 7 0 7 0 Main stream attribute data V start 7 0 from Vsync start edge to V active start edge RO A0 LSVStart 15 8 7 0 Main stream attribute d...

Page 13: ... Output Programming Video output path control registers are listed in the following table Reg Name bit Description Type Default Value 170 Reg_LMSwap 7 1 swap output direction MSB LSB R W 0 Reg_O16Bit 6 1 YCbCr422 output only 16bit width 0 YCbCr422 output is 24 20 bit width R W 0 Reg_OUTBit 5 4 00 output 8 bits per color channel 01 output 10 bits per color channel 10 output 12 bits per color channe...

Page 14: ... Reg_656FFRst 5 0 Reg_EnAVMuteRst 4 0 Reg_CSCSel 3 2 00 02 Reg_OutColMod 1 0 00 Output YCbCr444 video The output value should be bit Value 170 Reg_LMSwap 7 0 Reg_O16Bit 6 0 Reg_OUTBit 5 4 Reg_ColorDepth 3 2 Reg_PCLKDiv2 1 0 Reg_ChgSyncPol 0 0 176 Reg_SyncEmb 3 0 171 Reg_PGEn 7 0 Reg_DNFreeGo 6 x Reg_EnUdFilt 5 x Reg_EnDither 4 x Reg_VSyncPol 3 x Reg_HSyncPol 2 x Reg_ChSwap 1 x Reg_RBSwap 0 x 18F R...

Page 15: ...output value should be bit Value 170 Reg_LMSwap 7 0 Reg_O16Bit 6 0 Reg_OUTBit 5 4 00 Reg_ColorDepth 3 2 00 Reg_PCLKDiv2 1 0 Reg_ChgSyncPol 0 0 176 Reg_SyncEmb 3 1 171 Reg_PGEn 7 0 Reg_DNFreeGo 6 x Reg_EnUdFilt 5 x Reg_EnDither 4 x Reg_VSyncPol 3 x Reg_HSyncPol 2 x Reg_ChSwap 1 x Reg_RBSwap 0 x 18F Reg_OutDDR 7 0 Reg_2x656Clk 6 0 Reg_656FFRst 5 0 Reg_EnAVMuteRst 4 0 Reg_CSCSel 3 2 00 02 Reg_OutColM...

Page 16: ... bits R W 011100 198 Reg_Matrix22V 7 0 7 0 CSC matrix 22 low byte R W 00010110 199 Reserved 7 6 RO Reg_Matrix22V 13 8 5 0 CSC matrix 22 high bits R W 000100 19A Reg_Matrix23V 7 0 7 0 CSC matrix 23 low byte R W 01010110 19B Reserved 7 6 RO Reg_Matrix23V 13 8 5 0 CSC matrix 23 high bits R W 011111 19C Reg_Matrix31V 7 0 7 0 CSC matrix 31 low byte R W 01001001 19D Reserved 7 6 RO Reg_Matrix31V 13 8 5 ...

Page 17: ... 0x03 0x0A 0x0C 0x0C 0x0E Reg_Matrix23V 13 0 19A 0x56 0x6E 0x9F 0xAE 0x00 0x00 0x00 0x00 19B 0x3F 0x3F 0x3F 0x3F 0x00 0x00 0x00 0x00 Reg_Matrix31V 13 0 19C 0x49 0xAC 0xD9 0x49 0x00 0x4F 0x00 0x4F 19D 0x3D 0x3D 0x3C 0x3D 0x08 0x09 0x08 0x09 Reg_Matrix32V 13 0 19E 0x9F 0xD0 0x10 0x33 0x00 0x00 0x00 0x00 19F 0x3E 0x3E 0x3F 0x3F 0x00 0x00 0x00 0x00 Reg_Matrix33V 13 0 1A0 0x18 0x84 0x18 0x84 0xDB 0x1E ...

Page 18: ...ource select R W 11 RegI2S_CH2SEL 5 4 I2S channel 2 output source select R W 10 RegI2S_CH1SEL 3 2 I2S channel 1 output source select R W 01 RegI2S_CH0SEL 1 0 I2S channel 0 output source select R W 00 F9 RegHWMuteRate 7 0 7 0 Audio hardware mute rate low byte R W 001000 00 FA RegI2s_width 7 3 I2S word length select R W 11000 RegHWMuteRate 10 8 2 0 Audio hardware mute rate high bits R W 000 FB Reser...

Page 19: ...2 1 4 reg1B3 2 0 regEA 2 0 5 If mini mode set regF5 7 1 otherwise set is as 0 6 Enable audio output from IT6505 If require SPDIF output set regEB 3 0 If require I2S for 5 8 channel audio set regEB 2 1 0 0 If only require I2S audio with 1 4 channel set regEB 2 1 1 0 Audio Error If audio input have error audio will be automatic mute by IT6506 The interrupt of audio overflow underflow will be activat...

Page 20: ... bit 1 REPEATER RegCF 2 RegSetRepeater this bit bit 0 HDCP_CAPABLE RegB2 0 RegCPDesired 68029 BStatus 1 159 bit 2 link ingtegrity_fail loss of cipher synchronizationi bit 1 R0 Available bit 0 Ready HDCP repeater KSV FIFO ready Bstatus 2 LINK_INTEGRITY_FAILURE is indicated by the HW Bstatus 1 R0 _AVALILABLE is indicated by the HW Bstatus 0 READY is programed by RegCF 1 RegSetVReady 6802A BInfo 1 15...

Page 21: ...IT6506 PROGRAMMING GUIDE ITE Tech INC 18 2013 11 12 238 bInfo 7 0 R W 239 bInfo 15 0 R W ...

Page 22: ... 07 LSVBIDInt 7 VBID majority error interrupt W1C LSNAudInt 6 NAud majority error interrupt W1C LSMAudInt 5 Maud majority error interrupt W1C LSMVidInt 4 Mvid majority error interrupt W1C RegAFUflow 3 Audio fifo under flow RO RegAFOflow 2 Audio fifo over flow RO RegVFUflow 1 video fifo under flow RO RegVFOflow 0 video fifo over flow RO 08 LSAudMuteEnd 7 Audio mute end interrupt W1C LSAudMuteStart ...

Page 23: ... 0D LSL32NibbleErr 7 Lane 3 ECC 2 nibble error W1C LSL22NibbleErr 6 Lane 2 ECC 2 nibble error W1C LSL12NibbleErr 5 Lane 1 ECC 2 nibble error W1C LSL02NibbleErr 4 Lane 0 ECC 2 nibble error W1C LSL31NibbleErr 3 Lane 3 ECC 1 nibble error W1C LSL21NibbleErr 2 Lane 2 ECC 1 nibble error W1C LSL11NibbleErr 1 Lane 1 ECC 1 nibble error W1C LSL01NibbleErr 0 Lane 0 ECC 1 nibble error W1C 0E Reserved 7 6 RO R...

Page 24: ...eam received in the preceding port R W 0 Reg1LEDIDPret 6 0 receiver port 1 has no local EDID 1 receiver port 1 has a local EDID R W 0 Reg0ATPrecPort 5 0 port 0 is used for main isochronous stream 1 port 0 is used for secondary isochronous stream of main stream received in the preceding port R W 0 Reg0LEDIDPret 4 0 receiver port 0 has no local EDID 1 receiver port 0 has a local EDID R W 1 RegDSPort...

Page 25: ...2C repeat start R W 1 RegAUXINSel 6 0 delay auxin From auxrxctrl 1 delay auxin From clkbuf R W 0 RegDPCDReset 5 0 Normal 1 Reset DPCD FIFO R W 0 RegdisSelAudID 4 Disable select Audio Stream ID R W 0 Reg_newpkt_sel 3 New packet select R W 0 RegCmd_Filttap 2 Setting for I2C salve R W 0 RegCmd_Filttype 1 Setting for I2C salve R W 0 RegCmd_Deglitch 0 Setting for I2C salve R W 0 35 RegNoInfothresh 7 4 ...

Page 26: ... 1 0 Mpeg InfoFrame data byte count 9 8 RO 60 LSMpeg1PB 7 0 Mpeg InfoFrame packet payload byte 1 RO 61 LSMpeg2PB 7 0 Mpeg InfoFrame packet payload byte 2 RO 62 LSMpeg3PB 7 0 Mpeg InfoFrame packet payload byte 3 RO 63 LSMpeg4PB 7 0 Mpeg InfoFrame packet payload byte 4 RO 64 LSMpeg5PB 7 0 Mpeg InfoFrame packet payload byte 5 RO 65 LSGenPkt_0HB 7 0 General packet header byte 0 RO 66 LSGenPkt_1HB 7 0 ...

Page 27: ... Audio stream RO 97 LSHTotal 7 0 7 0 H total 7 0 RO 98 LSHTotal 15 8 7 0 H total 15 8 RO 99 LSHStart 7 0 7 0 H start 7 0 from Hsync start edge to H active start edge RO 9A LSHStart 15 8 7 0 H start 15 8 from Hsync start edge to H active start edge RO 9B LSHWidth 7 0 7 0 Main stream attribute data H active width 7 0 RO 9C LSHWidth 15 8 7 0 Main stream attribute data H active width 15 8 RO 9D LSVTot...

Page 28: ...HDCP SYNC DETECT RO LSAudMute 4 AudioMute_Flag RO LSNoVideo 3 NoVideoStream_Flag RO LSVdFrameMd 2 Interlace_Flag RO LSVdFieldTop 1 FieldID_Flag RO LSVBlank 0 VerticalBlanking_Flag RO B0 RegOtpCtrl 7 0 Otp encryption word selection for EMemory data R W 00101010 B1 RegOtpXor 7 0 Otp XOR value for EMemory data R W 10100101 B2 RegEMemWeakRd 7 EMemory weak read R W 1 RegEMemRWEn 6 EMemory Read Write en...

Page 29: ...CRMax 7 4 Max number of lost lock symbol in EQ phase If the number of lost lock symbol exceeds this setting CR_DONE in DPCD will be cleared Unit 16 times Default value 0000 16 times R W 0000 RegSymUnLockMax 3 0 Max number of lost lock symbol in normal operation after a successful Link Training If the number of lost lock symbol exceeds this setting CR_DONE CHANNEL_EQ_DONE and SYMBOL _LOCKED in DPCD...

Page 30: ...he time base Unit 37 04ns Default value 101011101000 is 100us R W 10101110 CE RegSetLnkStUpd 7 Force LINK_STATUS_UPDATED in DPCD R W 0 RegDBounceTime 6 3 Tx sense and Tx connected de bounce time Unit 150us Default value 0000 is 150us R W 0000 RegDisTrnVELmt 2 Disable Link Training 1 2V limitation R W 0 RegEnEQTimer 1 Enable EQ timeout timer R W 0 RegEnCRTimer 0 Enable CR timeout timer R W 0 CF Reg...

Page 31: ...or register 08 R W 11111111 E6 RegIntMask 23 16 7 0 Interrupt Mask 23 16 For Register 09 R W 11111111 E7 RegIntMask 31 24 7 0 Interrupt Mask 31 24 For Register 0A R W 11111111 E8 RegIntMask 39 32 7 0 Interrupt Mask 39 32 For Register 0B R W 11111111 E9 RegIntMask 47 7 Reserved For future use R W 1 RegIntMask 46 40 6 0 For Resister 0C 6 0 R W 1111111 EA RegDeMUXRST 7 DeMUX module reset R W 0 RegLKT...

Page 32: ...el 7 0 PCLKO PCLK 1 PCLKO not PCLK R W 0 RegErrCntDiv 6 5 00 div 1 01 div 2 10 div 4 11 div 8 R W 00 RegNormalCnt 4 1 enable 8b 10b error counter when normal state 0 disable 8b 10b error counter when normal state R W 0 RegErrThreshold 3 0 Error bit threshold for PRBS test R W 0000 F1 RegEnTest 7 NLPCM R W 0 RegMBusSel 6 0 write 4 link train data words to register 1 write 3 link train data words to...

Page 33: ...nel 1 output source select R W 01 RegI2S_CH0SEL 1 0 I2S channel 0 output source select R W 00 F9 RegHWMuteRate 7 0 7 0 Audio hardware mute rate low byte R W 00100000 FA RegI2s_width 7 3 I2S word length select R W 11000 RegHWMuteRate 10 8 2 0 Audio hardware mute rate high bits R W 000 FB Reserved 7 6 RO RegFSdec 3 0 RO FC RegI2CStCnt 7 0 Set I2C SCL frequency R W 00100001 FD Reserved 7 4 RegCheckAu...

Page 34: ...Force value for DPCD101H R W 00000001 2A RegDPCD102h 7 0 Force value for DPCD102H R W 00000000 2B RegDPCD103h 7 0 Force value for DPCD103H R W 00000000 2C RegDPCD104h 7 0 Force value for DPCD104H R W 00000000 2D RegDPCD105h 7 0 Force value for DPCD105H R W 00000000 2E RegDPCD106h 7 0 Force value for DPCD106H R W 00000000 2F RegDPCD107h 7 0 Force value for DPCD107H R W 00000000 30 6A hdcp68000 hdcp...

Page 35: ...ode enable R W 0 Reg_PGVActEd 10 8 5 3 Vertical active end high bits for PGDataPro module R W 010 Reg_PGVActSt 10 8 2 0 Vertical active start high bits for PGDataPro module R W 000 82 Reg_PGVActSt2nd 7 0 7 0 R W 11111111 83 Reg_PGVActEd2nd 7 0 7 0 R W 11111111 84 Reg_PGVActEd2nd 10 8 5 3 R W 111 Reg_PGVActSt2nd 10 8 2 0 R W 111 85 Reg_PGHTotal 7 0 7 0 Horizontal total low byte for PGDataPro module...

Page 36: ... R W 011101 9E Reg_Matrix32V 7 0 7 0 CSC matrix 32 low byte R W 10011111 9F Reserved 7 6 RO Reg_Matrix32V 13 8 5 0 CSC matrix 32 high bits R W 011110 A0 Reg_Matrix33V 7 0 7 0 CSC matrix 33 low byte R W 00010110 A1 Reserved 7 6 RO Reg_Matrix33V 13 8 5 0 CSC matrix 33 high bits R W 000100 A2 Reserved 7 4 RO RegABSwap 3 R W 0 RegLMSwapB 2 R W 0 RegRBSwapB 1 R W 0 RegDualFFRst 0 R W 0 A5 Reg_VCLK_ST0 ...

Page 37: ... bias generator into power down mode R W 0 Reg_PWDIPLL 0 PLL powerdown PWDB 0 will put PLL into power down mode except current bias R W 0 B3 Reg_RSTCDR 7 Reset digital CDR block R W 0 Reg_RSTFIFO 6 Reset 8b 10b FIFO R W 0 Reg_RSTAFE 5 Reset all AFE R W 0 Reg_RSTCPLL 4 Reset CDR PLL R W 0 Reg_RSTIPLL 3 Reset interpolation PLL R W 0 Reg_RSTAPLL 2 Reset Audio PLL R W 0 Reg_RSTVPLL 1 Reset Video PLL R...

Page 38: ... R W 0 RegTestPtnReq 1 0 no test pattern requested 1 test pattern requested R W 0 RegTestLkTrain 0 0 no link training test requested 1 link training test requested R W 0 E1 RegTestLkRate 7 0 06h 1 62Gbps 0Ah 2 7Gbps R W 00000110 E2 Reserved 7 5 RO RegTestLaneCnt 4 0 1h one lane 2h two lanes 4h four lanes R W 00001 E3 M0 7 0 7 0 M0 Byte0 RO 00000000 E4 M0 15 8 7 0 M0 Byte1 RO 00000000 E5 M0 23 16 7...

Page 39: ...ponent R W 00000000 FA RegTestCRCGY 15 8 7 0 R W 00000000 FB RegTestCRCBCb 7 0 7 0 Stores the 16 bit CRC value of the B or Cb component R W 00000000 FC RegTestCRCBCb 15 8 7 0 R W 00000000 FD Reserved 7 5 RO RegTestCRCSup 4 0 CRC not supported by Sink Device 1 CRC supported by Sink Device R W 0 RegTestCRCCnt 3 0 4 bit wrap counter which increments each time the reg1F7h reg1FCh are updated Reset to ...

Page 40: ...FIFO 7 0 7 0 KSV3FIFO Byte0 R W 00000000 220 KSV3FIFO 15 8 7 0 KSV3FIFO Byte1 R W 00000000 221 KSV3FIFO 23 16 7 0 KSV3FIFO Byte2 R W 00000000 222 KSV3FIFO 31 24 7 0 KSV3FIFO Byte3 R W 00000000 223 KSV3FIFO 39 32 7 0 KSV3FIFO Byte4 R W 00000000 224 V0 7 0 7 0 V0 Byte0 R W 00000000 225 V0 15 8 7 0 V0 Byte1 R W 00000000 226 V0 23 16 7 0 V0 Byte2 R W 00000000 227 V0 31 24 7 0 V0 Byte3 R W 00000000 228...

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