Copyright, 2004 Imaging Solutions Group
of NY
, Inc., All Rights Reserved
Revision 2.1 Subject to change without notice.
22 of 33
Address : 0x420 (VVDLY)
Data format : B4
Default Value : 02h
7
6
5
4
3
2
1
0
not used
VVDLY(3:0)
VVDLY :
Video Valid Delay. The value in this register is used to move the video relative to
the video valid signal internal to the FPGA.
Address : 0x448 (CLKCR)
Data format : U5
Default Value: 0h
7 6 5 4 3 2
1
0
not used
INV CLKDIV(3:0)
INV:
When this bit is set, the sensor clock is inverted.
CLKDIV :
Clock Divider. The sensor base clock rate is 48Mhz for Micron and
48Mhz for IBIS. This value is R/W.
Address : 0x824 (DGAIN)
Data format : U4.4
Default Value : 10h
7
6
5
4
3
2
1
0
DGAIN(7:0)
DGAIN :
Digital Gain. The input video is multiplied by this value. The result is truncated
to 1023. The range of DGAIN is 0 to 15.9375 in steps of 1/16. This value is R/W.
Summary of Contents for LW-3-S-1394
Page 32: ......
