Copyright, 2004 Imaging Solutions Group
of NY
, Inc., All Rights Reserved
Revision 2.1 Subject to change without notice.
21 of 33
Address : 0x410 (RTGDLY)
Data format : U16
Default Value: 00h
15
14
13
12
11
10
9
8
RTGDLY(15:8)
7
6
5
4
3
2
1
0
RTGDLY(7:0)
RTGDLY :
This 16 bit Value is used to program the delay between video frames in continues
trigger
Mode. A delay between 0 and 341ms in 5.21us steps can be achieved. The
default value is 0.
Address : 0x414 (PWM)
Data format : U8
Default Value : 80h
7 6 5 4 3 2 1 0
PWM(7:0)
PWM :
PWM Duty Cycle. This register controls the duty cycle of the 13Khz PWM
signal fed to the illumination system. FFh = 100%, 80h = 50%, 00h = .4%.
Address : 0x41c (VERREG)
Data format : B8
Default Value : 0Bh
7
6
5
4
3
2
1
0
VERREG(7:0)
VERREG :
The value in this register is used to identify the FPGA firmware revision.
Summary of Contents for LW-3-S-1394
Page 32: ......
