IGEP
TM
SMARC iMX6
Hardware Reference Manual
ISEE 2007 S.L. All rights reserved, IGEP is a registered trademark from ISEE 2007 S.L. The following is provided for informational purposes only.
NIF:ESB64377005 Document:
MAN-IGEP0046-001
/ Revision:
1.3
/ Date:
23/06/2016
31
4.15
PCIe
PCI Express (or PCIe) is a scalable, point-to-point serial bus interface commonly used for high speed data
exchange between a PCIe host, or root, and a target device. It is scalable in the sense that there may be link
widths, per the PCIe specification, that are x1, x2, x4, x8, x16 or x32. SMARC currently calls out only x1
operation. A PCIe link is AC coupled, but the coupling capacitors are defined in the SMARC specification to be
on the Module, for only PCIe transmit pair.
The next figure show how to connect PCIe SMARC pins to Mini-PCIe connector (page 75 of SMARC Design
Guide).
Figure 24 PCIe connection example
Pin
Volt
Level
Dev
Pin
Main Function
Main
MUX
Type
Fixed
Function
Comments
P83
DIF
D7
PCIE_
0
LVDS
TIA/EIA-644
YES
Differential PCIe Link A reference clock output DC
c
P84
DIF
C7
PCIE_A_REFCK-
0
LVDS
TIA/EIA-644
YES
Differential PCIe Link A reference clock output DC
coupled -
P86
DIF
B2
PC
0
LVDS
TIA/EIA-644
YES
Differential PCIe Link A receive data pair 0 +
P87
DIF
B1
PCIE_A_RX-
0
LVDS
TIA/EIA-644
YES
Differential PCIe Link A receive data pair 0 -
P89
DIF
B3
PC
0
LVDS
TIA/EIA-644
YES
Differential PCIe Link A transmit data pair 0 +. This
signal has a 0.1 uF coupling capacitor.
P90
DIF
A3
PCIE_A_TX-
0
LVDS
TIA/EIA-644
YES
Differential PCIe Link A transmit data pair 0 -. This
signal has a 0.1 uF coupling capacitor.
P74
3V3
U24
PCIE_A_PRSNT#
5
IN
YES
PCIe Port A present input. This signal has a 4K7 PU
resistor.
P75
3V3
F15
PCIE_A_RST#
5
OUT
NO
PCIe Port A reset output
P78
3V3
T21
PCIE_A_CKREQ#
5
IN
YES
PCIe Port A clock request input. This signal has a 4K7
PU resistor.
Table 19 PCIe pins
