IGEP
TM
SMARC iMX6
Hardware Reference Manual
ISEE 2007 S.L. All rights reserved, IGEP is a registered trademark from ISEE 2007 S.L. The following is provided for informational purposes only.
NIF:ESB64377005 Document:
MAN-IGEP0046-001
/ Revision:
1.3
/ Date:
23/06/2016
10
3.2
IGEP
TM
SMARC iMX6 FEATURES
Feature
IGEP
SMARC
iMX6Quad
IGEP
SMARC
iMX6Dual
IGEP
SMARC
iMX6DualLite
IGEP
SMARC
iMX6Solo
ARM CPU
4x NXP iMX6 ARM
Cortex–A9TM up to
1.2GHz
L1 Instruction cache:
32 KB per core
L1 Data cache: 32 KB
per core
L2 cache: 1 MB
NEON
TM
SIMD
Coprocessor per core
PTM per core
2x NXP iMX6 ARM
Cortex–A9TM up to
1.2GHz
L1 Instruction cache:
32 KB per core
L1 Data cache: 32 KB
per core
L2 cache: 1 MB
NEON
TM
SIMD
Coprocessor per core
PTM per core
2x NXP iMX6 ARM
Cortex–A9TM
up
to
1GHz
L1 Instruction cache: 32
KB per core
L1 Data cache: 32 KB per
core
L2 cache: 512 KB
NEON
TM
SIMD
Coprocessor per core
PTM per core
1x NXP iMX6 ARM
Cortex–A9TM up to
1GHz
L1 Instruction cache:
32 KB
L1 Data cache: 32 KB
L2 cache: 512 KB
NEON
TM
SIMD
Coprocessor
PTM
2D/3D graphics
acceleration
Vivante GC2000 GPU 3D
Vivante GC320 GPU 2D (Composition)
Vivante GC355 GPU 2D (Vector Graphics)
OpenGL ES 3.0, OpenCL 1.1 EP and Open VG
1.1 support
Vivante GC880 GPU 3D
Vivante GC320 GPU 2D (Composition)
GPU 2D (Vector Graphics) emulated on GPU 3D
OpenGL ES 2.0 support
Video
acceleration
Video acceleration: H.264, H.263, MPEG-2 and
MPEG-4
Video encoder/decoder dual 1080p @ 60 fps
2x IPU
Video acceleration: H.264, H.263, MPEG-2 and
MPEG-4
Video encoder/decoder 1080p @ 60 fps
1x IPU
Camera
Interface
MIPI CSI-2 (4 lanes)
MIPI CSI-2 (2 lanes)
Table 3 IGEP
TM
SMARC iMX6 Proc
essor
Feature
Specifications
RAM Memory
256 MB up to 4 GB DDR3-1066 SDRAM
Storage
No flash up to 64 GB eMMC
Table 4 Memory and Storage
Feature
Specifications
Power to SMARC-314 connector
Supply Voltage (VIN) from 4.75 V to 5.25 V DC
Table 5 Power
