3280-dda.ib.doc
page 9 of 16
23/07/2002
Logic processing, reclocking and AIS detection:
The main logic processing, reclocking, error detection and operational interfacing are all performed by logic circuits
within U 4, which is a custom-programmed large scale logic array. The internal logic and functions of this IC are too
complex to describe in detail and the following is intended as a guide to function only.
Data loss detection:
Valid data is deemed to be present at the module input when 120 or more data pulses have been received in 512
nominal clock periods at the G.703 data bit rate specified for the DDA. In order for the data pulse to be counted,
more than 60% of the minimum anticipated data pulse must be present.
If less than 120 data pulses are counted over a period of 512 clock pulses then the data signal is deemed to be invalid
and the data loss flag is set.
If the area of a given pulse is less than 60% of the minimum anticipated (or acceptable) data pulse, after line
equalisation and shaping, then that pulse is not considered as a valid input to the count.
In any of these cases the
Data Loss
LED on the front panel of the module will light and the general alarm relay
output will be activated connecting the general alarm output contact to ground.
AIS detection:
The data processor will detect an incoming AIS (Alarm Indication Signal) (a series of >2048 1’s) and will set the
AIS flag and the general alarm relay output will be activated connecting the general alarm output contact to ground.
Note however that when data errors or no data is detected that the DDA-3280 does not generate an outgoing AIS
data stream to the data outputs.
The AIS alarm system may be disabled by a link on the main board LK 1. This prevents the AIS detection from
operating the automatic changeover function when used in handshake configuration and prevents AIS from setting
the general alarm output. The AIS detection circuit will, however, still provide AIS indication, on the front panel
LED, if AIS is detected.
The AIS disable link does not effect the general alarm being activated by data or signal loss as described above.
Power on reset:
When power is applied to the unit, U 6 generates a
power on reset
signal. This signal causes the processing circuit to
examine its current status and connections and restore operation to its state prior to power failure.
If the DDA is connected for stand-alone operation all alarms will be reset and normal operation will resume. If an
AIS signal is present on the data input or data is outside the prescribed limits outlined above then the general alarm
will be activated after the normal detection period has elapsed from the P.O.R. signal being initiated.
For operation in handshake mode see
Handshake
operation description.
ARA in & urgent alarm out.
These facilities are not enabled at this time.
Data signal output drivers.
The recve and -ve mark signals are bussed to output drivers U 7 to 10.
Each output driver consists of three inverters operating in parallel in order to obtain a high current output capability
for driving the output transformer without stressing any individual amplifier.
Diodes are connected across the transformer primary to ground and the inverter output to +5V to prevent any back
EMF from causing damage to the drivers. The resistors between the output drivers and the output transformer set the
correct output operating pulse amplitude to
±
2.37 V measured at the output connectors.
Note that the
Mon. Output
on the front panel of the module is obtained in the same manner as the outputs on the rear
of the module.
IRT
Communications
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