User Guide: Technical Reference
SECTION 2
ioLink 4
SYSTEM COMPONENTS
PRELIMINARY
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were not present at installation that may impact the transmission path, so the user can take corrective
action.
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Circuitry for Forward Error Correction (FEC)
Once the link is established, the FEC works in the following manner:
“All user data bits are encoded by the transmitting side’s modem unit and sent to the
receiver. The receiving modem unit uses an algorithm along with the previously
received set of bits to determine the possible valid configurations for the current set of
bits. If the current set of bits are not of a valid form, an alarm is registered (see “FEC
decoder not locked” in section IV, Network Management). Since the receiving
modem unit knows all the possibilities of what the current set of bits should be, it can
then use this information along with the FEC algorithm to correct most bit errors that
may have been introduced during transmission.”
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Influence of FEC on Bit Error Rate (BER)
Forward Error Correction is used in the
ioLink 4
to reduce the number of bit errors
encountered in normal wireless transmission. To do this, the transmitting unit uses the
previous block of data to predict what form the current data signal should have so that the
receiver may use the redundant signal to find any errors in the original signal and correct
them. Depending on the nature and periodicity of the errors, FEC may not always detect and
correct every error that is introduced into the signal. If the errors are singular in the signal, it is
easier for the error detection circuitry to find and correct the errors. If the errors are
introduced in large bursts, it is more likely that the circuitry will be unable to correct all of the
errors.
The following example shows the difference between the two cases. Both link A and link B may be
experiencing a total of 3,600 uncorrected errors every hour, but the post-FEC BER for the two links may
be quite different. If link A receives 1 error every second, the FEC circuitry should be able to correct all of
the errors as there are few errors at any point in time. If link B receives a burst of 1,200 errors every half-
hour on the half-hour, the FEC circuitry will have more difficulty correcting the errors because of the high
volume of errors introduced. Notice that both links get an average of 3,600 errors per hour, but the
distribution in which they get them affects the ability of the FEC to find and correct those errors. Link A will
have a post-FEC BER of nearly zero while Link B’s post-FEC BER will be around 10(-7).
