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Application Note 1664

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FIGURE 3. BOTTOM LAYER

PCB Layout 

 (Continued)

Summary of Contents for ISL97683

Page 1: ...asily adjusting the LED maximum DC current please refer to the evaluation board schematic on page 2 for more details LED dimming frequency and duty cycle 1 As mentioned in Step 4 when the shunt on JP20 is connected to the upper position and the FPWM DPWM pin is connected to VDC the device enters direct PWM mode which means both the LED dimming frequency and the duty cycle are synchronized with the...

Page 2: ...nF 50V R5 1M R6 0 R7 Open R8 5k R9 10k C15 8 2nF C3 33pF TP1 LX TP2 VOUT TP3 CH1 TP4 CH2 TP5 CH3 TP7 VDC P5 AGND P6 AGND P7 AGND P8 AGND P9 PGND P10 PGND 2 layer board Connect top layer PGND and bottom layer AGND at one single point through the via on the thermal pad under the chip F1 2A Fuse JP14 R11 100k R10 0 R13 Open R12 27k JP15 JP16 JP17 ISL97683EVAL1Z Rev A EN can be connected in the follow...

Page 3: ...Application Note 1664 3 AN1664 0 December 13 2011 PCB Layout FIGURE 2 TOP SILKSCREEN LAYER AND TOP LAYER ...

Page 4: ...Application Note 1664 4 AN1664 0 December 13 2011 FIGURE 3 BOTTOM LAYER PCB Layout Continued ...

Page 5: ... X7R capacitors C3 33pF 603 C4 1µF 16V 603 C5 4 7µF 50V 1210 Murata GRM32ER71H475KA88L C6 4 7µF 50V 1210 C7 Place Holder 1210 Not Populated C8 Place Holder 1210 C9 100pF 50V 603 General purpose C10 3 6nF 50V 603 Ceramic X5R X7R capacitors C11 1nF 50V 603 C12 1nF 50V 603 C13 1nF 50V 603 C14 Place Holder 603 C15 8 2nF 603 F1 2A Fuse 1206 Bel Fuse Inc C1Q 2 U1 QFN16 3MM Intersil ISL97682 3 4 JP2 JP19...

Page 6: ...l com AN1664 0 December 13 2011 TP3 CH1 TEST POINT TP4 CH2 TEST POINT TP5 CH3 TEST POINT TP6 CH4 TEST POINT TP7 VDC TEST POINT TP8 RSET TEST POINT TP9 FSW PHS TEST POINT P5 AGND TEST POINT Keystone Electronics P6 AGND TEST POINT 5011 P9 PGND TEST POINT P1 PVIN POWERPOST Mill Max P2 VIN POWERPOST 3156 1 00 00 00 00 08 0 P3 EN POWERPOST P4 PWMI POWERPOST P7 AGND POWERPOST P8 AGND POWERPOST P10 PGND ...

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