Application Note 1664
2
AN
1664
.0
De
ce
mbe
r 1
3
, 2
01
1
1
2
3
4
5
6
A
B
C
D
6
5
4
3
2
1
D
C
B
A
Title
Number
Revision
Size
B
Date:
10-Oct-2011
Sheet of
File:
C:\ISL97682_3_4\ISL97682EVAL1Z_RevA.ddb
Drawn By:
L1
15uH
D1
PMEG6030
1
3
2
SW1
1
3
2
SW2
R1
150k
R2
100k
When
SW1=SW2=1: Fsw=1.2MHz, WITH phase shift
SW1=SW2=3: Fsw=600KHz, WITH phase shift
SW1=1, SW2=3: Fsw=1.2MHz, WITHOUT phase shift
SW1=3, SW2=1: Fsw=600KHz, WITHOUT phase shift
C1
10uF/50V
C2
0.1uF/50V
P1
PVIN
C4
1uF/16V
P3
EN
P4
PWMI
VDC
C5
4.7uF/50V
C6
4.7uF/50V
C7
NC
C8
NC
LED1
LED13
LED25
LED2
LED14
LED26
LED3
LED15
LED27
LED4
LED16
LED28
LED5
LED17
LED29
LED6
LED18
LED30
LED7
LED19
LED31
LED8
LED20
LED32
LED9
LED21
LED33
LED10
LED22
LED34
LED11
LED23
LED35
LED12
LED24
LED36
JP2
I_OUT
JP3
JP4
JP5
R4
10k
R3
357k
C10
3.3nF/50V
C9
100pF/50V
JP7
JP8
JP9
JP11
JP12
C13
1nF/50V
C12
1nF/50V
C11
1nF/50V
R5
1M
R6
0
R7
Open
R8
5k
R9
10k
C15
8.2nF
C3
33pF
TP1
LX
TP2
VOUT
TP3
CH1
TP4
CH2
TP5
CH3
TP7
VDC
P5
AGND
P6
AGND
P7
AGND
P8
AGND
P9
PGND
P10
PGND
2-layer board. Connect top layer PGND and bottom
layer AGND at one single point through the via on
the thermal pad under the chip.
F1
2A Fuse
JP14
R11
100k
R10
0
R13
Open
R12
27k
JP15
JP16
JP17
ISL97683EVAL1Z
Rev. A
EN can be connected in the following ways to
enable/disable the device:
(1) Connected it to VIN directly on JP1 to enable
(2) Connected it to GND directly on JP1 to disable
(3) Directly apply external voltage on P3(EN) to
enable/disable the device without putting shunt on JP1.
JP2: For measuring total output current
JP3-JP6: For measuring current on CH1-CH4 respectively
JP7-JP10, JP13-JP16: For easy configuration of 8x LED or 10x
LED per string
JP19
1 2
WR
TP8
RSET
TP9
FSW/PHS
P2
VIN
VDC
1
3
2
JP1
1
3
2
JP20
VDC
NC
16
AGND
1
CO
M
P
2
RSE
T
3
FSW
4
PWMI
5
EN
6
VIN
7
FPWN/DPWM
8
LX
9
PGND
10
VDC
11
OVP
12
CH1
13
CH2
14
CH3
15
ISL97683
U1
XAL6060-153MEB
FIGURE 1. EVALUATION BOARD SCHEMATIC
