User Guide 083
UG083.0
July 25, 2016
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2
FIGURE 3. BLOCK DIAGRAM
SCL
SDA
A
VDD
D
VDD
I
2
C
INTERFACE
ANALOG
POWER
SUPPLY
DIGITAL
POWER
SUPPLY
REF
IN
RAM
14x10
CONTROL
BYTE
EEPROM
V
COM
DAC
10
GND
DAC15
GND
REF
IN
WP
WP: ACTIVE LOW
OUT1
OUT2
V
COM
AMPLIFIER
DAC1
10
10
DAC2
OUT3
10
DAC3
OUT4
OUT5
DAC4
10
10
DAC5
OUT6
10
DAC6
OUT7
OUT8
DAC7
10
10
DAC8
OUT9
10
DAC9
OUT10
OUT11
DAC10
10
10
DAC11
OUT12
10
DAC12
OUT13
OUT14
DAC13
10
10
DAC14
GND
OUTCOM
INN_COM
DAC/OUTx
BUFFER
A
VDD
_
AMP
GND
A0
+
-
