Interphase iSPAN 5535 PRI, User Manual

Page: 35 / 168

Chapter 2: Installing the Hardware
iSPAN PRI PCI ISDN Users Guide
15
Requirements for MVIP Bus Electrical
Termination
For systems with five or fewer MVIP bus connections and less
than 90 pF load on the clock lines, it is adequate to place the
circuit board that is the master clock source at one end of the
cable and electrically terminate the MVIP bus only on the
circuit board located at the other end of the cable.
N
OTE
The
i SPAN
-PRI adapter is generally the master clock
source, because it is connected to the network. In this
case, place the
i SPAN
-PRI adapter at one end of the
cable.
On systems with more than five MVIP bus connections or
more than 90 pF of load on the clock lines, both ends of the
cable must be electrically terminated. No other boards should
be electrically terminated.
If the
i
SPAN
-PRI adapter is at one of the MVIP cable ends,
you must set the dip switches to their ON position (down) to
complete the required electrical termination. Consult the
relevant manuals for other MVIP adapters to correctly
configure their specific electrical termination.
If you do not connect the
i SPAN
-PRI to an MVIP bus, you can
leave the dip-switches, located close to the 40-pin double-row
right-angled header, on any position.