Intermec 869 RFID Reader, Service Instructions Manual

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Theory of Operation
—
Chapter 2
15 869 RFID Reader Service Instruction Manual
Parallel I/O Peripherals
A/D CONVERTER
The TI (THS1206) is a 12-bit, 6 MSPS, 2 channel (differential) or 4
channel (single ended), simultaneous sampling, pipelined, FIFO'd, SAR
A/D that has a 12bit parallel digital interface. The parallel interface directĆ
ly interfaces to the DSP's memory map and supports DMA transfer of
data.
CPLD
The Xilinx (XCR3128XL) CPLD contains the registers that control the
radio control signals, LED's, SPI device selection, and JTAG control sigĆ
nals to the Lattice anti-aliasing filters. The CPLD also handles the voltage
level conversion for the input GPIO's, the polarity inversion of the UART
IRQ's, and the address decoding logic for the external peripherals on the
parallel bus (including the registers within the CPLD).
UART
The XR16C2850 is a dual UART that supports a 128 byte FIFO, and data
rates up to 230 Kbit/s. The UART interfaces to the DSP via the parallel
bus. The 2
nd
channel can be used for a debug port or future interface opĆ
tion.
RF Section
The RF section simultaneously transmits and receives using one antenna.
The RF power control function is a software semi-closed loop control that
uses calibration data stored in non-volatile RAM.