Intermec 869 RFID Reader, Service Instructions Manual

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Theory of Operation
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Chapter 2
13 869 RFID Reader Service Instruction Manual
Digital Architecture
Overview
The processor used is a TI TMS320C5510 DSP. It is a low cost, high perĆ
formance processor with low power consumption, sufficient peripherals for
the application, and a DSP architecture that is ideal for filter operations. It
has 160K x 16-bit no wait-state On-Chip RAM and a PLL to enable an
external oscillator to provide up to a 160 MHz internal cycle speed.
The data computation unit of the CPU contains a 40-bit Barrel Shifter,
40 and 16 bit ALU's, four 40-bit Accumulators, two17x17-bit multiplier
with dedicated accumulator (MAC) which effectively boosts the MIPS caĆ
pability to 320, and many other features tailored for DSP operations.
The bus structure is a Harvard Architecture style with one Program
Memory bus and five Data Memory buses. Additional peripherals include
an external memory interface supporting SDRAM, three McBSP (specialĆ
ized serial interfaces), two 20-bit timers, a six-channel DMA controller,
and eight GPIO.
Two of the McBSP's are configured for SPI mode and are used to interface
the DSP to the DAC, RF PLL, anti-aliasing filters, and EEPROM. The
third McBSP is dedicated to the ADC to provide the sample rate clock.
The key external peripherals that impact performance are a 12 bit dual
channel DAC, 12 bit 2/4 channel ADC, 2MBx32 bit SDRAM, and two
programmable anti-aliasing filters.
The 6 MSPS ADC has a sufficient sampling rate to support the 4x return
link data rate of the G2 tags. The 12 bit DAC provides sufficient resoluĆ
tion for the filtered modulation which is required to meet the spectral
mask requirements for European regulations.
The 2Mx32 bit SDRAM provides external, low cost high speed memory
for supporting large quantities of tags and also provides room for adding
future software features.