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CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charge as high as 4000V
readily accumulate on the human body and test equipment and can discharge
without detection. Although the AD7819 features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges, Therefore, proper ESD precaution are recommended to avoid performance degradation or loss of
functionality.
PIN FUNCTION DESCRIPTION
Pin No. Mnemonic Description
1
V
REF
Reference Input, 1.2V to V
DD
.
2
V
IN
Analog Input, 0V to V
REF
.
3
GND
Analog and Digital Ground.
4
CONVST
Convert Start. A low-to-high transition on this pin initiates a 1.5 µs pulse on an
internally generated CONVST signal. A high-to-low transition on this line initiates the
conversion process if the internal CONVST signal is low. Depending on the signal on
this pin at the end of a conversion, the AD7819 automatically powers down.
5
CS
Chip Select. This is a logic input. CS is used in conjunction with RD to enable outputs.
6
RD
Read Pin. This is a logic input. When CS is low and RD goes low, the DB7-DB0 leave
their high impedance state and data is driven onto the data bus.
7
BUSY
ADC Busy Signal. This is a logic output. This signal goes logic high during the
conversion process.
8-15
DB0-DB7
Data Bit 0 to 7. These outputs are three-state TTL-compatible.
16
V
DD
Positive power supply voltage, 2.7V to 5.5V.
PIN CONFIGURATION DIP/SOIC
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Linearity Error(LSB)
Package Description
Package Option
AD7819YN
± 1 LSB
Plastic DIP
N-16
AD7819YR
± 1 LSB
Small Outline IC
R-16A
AD7819YRU
± 1 LSB
Thin Shark Small
RU-16
Outline (TSSOP)
ABSOLUTE MAXIMUM RATINGS*
V
DD
to DGND ..............................................................................................................................-0.3V to + 7V
Digital Input Voltage to DGND
(CONVST, RD, CS) ...............................................................................................................-0.3V, V
DD
+ 0.3V
Digital Output Voltage to DGND
(BUSY, DB0-DB7) .................................................................................................................-0.3V, V
DD
+ 0.3V
REF
IN
to AGND ......................................................................................................................-0.3V, V
DD
+ 0.3V
Analog Input ..........................................................................................................................-0.3V, V
DD
+ 0.3V
Storage Temperature Range.................................................................................................-65
to + 150°C
Junction Temperature ........................................................................................................................... 150°C
Plastic DIP Package, Power Dissipation .............................................................................................450mW
JA
Thermal Impedance...................................................................................................................105°C/W
Lead Temperature, (Soldering 10 sec)................................................................................................260°C
SOIC Package, Power Dissipation ......................................................................................................450mW
JA
Thermal Impedance .....................................................................................................................75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) ....................................................................................................................215°C
Infrared (15 sec)............................................................................................................................220°C
SSOP Package, Power Dissipation .....................................................................................................450mW
JA
Thermal Impedance ...................................................................................................................115°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) ....................................................................................................................215°C
Infrared (15 sec).............................................................................................................................220°C
Figure 1. Load Circuit for Digital Output Timing Specifications
Summary of Contents for GEQ-1231D
Page 15: ...27 26...
Page 16: ...29 28...
Page 17: ...31 30 BLOCK DIAGRAM WIRING DIAGRAM...
Page 18: ...32...
Page 19: ...34 33 SCHEMATIC DIAGRAM GEQ 1231D FRONT B D...
Page 20: ...36 35 GEQ 2231D FRONT B D 1 2...
Page 21: ...38 37 GEQ 2231D FRONT B D 2 2...
Page 22: ...40 39 IN OUT B D...
Page 23: ...42 41 POWER B D...
Page 24: ...44 43 SHT B D 1 4...
Page 25: ...46 45 SHT B D 2 4...
Page 26: ...48 47 SHT B D 3 4...
Page 27: ...50 49 SHT B D 4 4...
Page 28: ...52 51 EXPLODED CIEW OF CABINET CHASSIS MACHANICAL PARTS LIST...
Page 29: ...54 53...
Page 30: ...56 55 ASS Y DRAWING...
Page 31: ...58 57...
Page 32: ...NOTE...