Inter-m GEQ-1231D Service Manual Download Page 29 | Manualshive

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Inter-m GEQ-1231D Service Manual Download Page 29

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Summary of Contents for GEQ-1231D

Page 1: ...www inter m com MADE IN KOREA 2003 2 9017100300 SERVICE MANUAL S T E R E O D U A L 3 1 B A N D G R A P H I C EQUALIZER GEQ 1231D 2231D...

Page 2: ...l multiplexer The binary code placed on the A B and C select lines determines which one of the eight switches is on and connects one of the eight inputs to the common output FEATURES Wide analog input...

Page 3: ...s otherwise noted 2 TRUTH TABLES LOGIC DIAGRAMS CONNECTION DIAGRAMS Pin Assignments for DIP SOIC SOP and TSSO Input Inh C B A ON Channel H L L L L L L L L X L L L L H H H H X L L H H L L H H X L H L H...

Page 4: ...337 1 14 Pin Plastic TSSOP Type I 40 C to 125 C 74LV164PW 74LV164PW DH SOT402 1 74LV164 8 bit SERIAL IN PARALLEL OUT SHIFT REGISTER FEATURES Wide operating voltage 1 0 to 5 5V Optimized for Low Voltag...

Page 5: ...e package DIP in a 6 lead 0 15 wide narrow body small outline IC SOIC and in a 16 lead narrow body thin shrink small outline package TSSOP AD7819 2 7V to 5 5V 200 kSPS 8 bit SAMPLING ADC FEATURES 8 Bi...

Page 6: ...ess 8 15 DB0 DB7 Data Bit 0 to 7 These outputs are three state TTL compatible 16 VDD Positive power supply voltage 2 7V to 5 5V PIN CONFIGURATION DIP SOIC Stresses above those listed under Absolute Ma...

Page 7: ...namic Range S N 100dB Digital HPF for offset cancellation Input PGA with 8dB gain 0 5dB step Input DATT with 72dB att I F format MSB justified or I2 S 24bit 2ch DAC 128 x Oversampling 24bit 8 times Di...

Page 8: ...Lead MQFP or 196 Ball Mini BGA Package 3 3 Volt Operation Flexible Data Formats and 40 Bit Extended Precision 32 Bit Single Precision and 40 Bit Extended Precision IEEE Floating Point Data Formats 32...

Page 9: ...5 0 of the bus Pull up resistors on unused DATA pins are not necessary MS3 0 I O T Memory Select Lines These lines are asserted as chip selects for the corresponding banks of external memory Internal...

Page 10: ...n allows the core processor of an ADSP 21065L bus slave to interrupt background DMA transfers and gain Pin Type Function access The ADSP 21065L deasserts ACK as an output to add wait states to a synch...

Page 11: ...pply nominally 3 3V dc 33 pins GND G Power Supply Return 37 pins NC Do Not Connect Reserved pins that must be left open and unconnected 7 CLOCK SIGNALS The ADSP 21065L can use an external clock or a c...

Page 12: ...DATA9 97 DATA10 98 DATA11 99 GND 100 DATA12 101 DATA13 102 NC 103 NC 104 DATA14 105 VDD 106 GND 107 DATA15 108 DATA16 109 DATA17 110 VDD 111 DATA18 112 DATA19 113 DATA20 114 GND 115 NC 116 DATA21 117...

Page 13: ...Output Attenuator in 3dB Steps 20dBu to 2dBu and Unity Gain Mode GRAPHIC EQUALIZER 31 Band 1 3 Octave Interpolating Constant Q Filter Bank Selectable Boost Cut Range 12dB 6dB and 0 to 12dB 0 to 6dB i...

Page 14: ...532 DMP 8 JRC 5532DD J3 J5 S30100007231 RES TF 0 1 10W 2012 0 R614 R628 630 S30100007121 RES TF 0 1 16W 1608 0 R503 504 R523 524 S30331505121 RES MF 1 5K F 1 16W 1608 1 5K 1 R658 R680 681 S30101017231...

Page 15: ...27 26...

Page 16: ...29 28...

Page 17: ...31 30 BLOCK DIAGRAM WIRING DIAGRAM...

Page 18: ...32...

Page 19: ...34 33 SCHEMATIC DIAGRAM GEQ 1231D FRONT B D...

Page 20: ...36 35 GEQ 2231D FRONT B D 1 2...

Page 21: ...38 37 GEQ 2231D FRONT B D 2 2...

Page 22: ...40 39 IN OUT B D...

Page 23: ...42 41 POWER B D...

Page 24: ...44 43 SHT B D 1 4...

Page 25: ...46 45 SHT B D 2 4...

Page 26: ...48 47 SHT B D 3 4...

Page 27: ...50 49 SHT B D 4 4...

Page 28: ...52 51 EXPLODED CIEW OF CABINET CHASSIS MACHANICAL PARTS LIST...

Page 29: ...54 53...

Page 30: ...56 55 ASS Y DRAWING...

Page 31: ...58 57...

Page 32: ...NOTE...

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