Table 12.
Intel Stratix 10 MX HBM2 Required Clock Inputs
Clock
Description
Clock Guidelines
core_clk_iopll_ref_clk_clk
LVDS differential input clock used to
generate the fabric core clock.
You can place this clock on any I/O PLL
refclk
input pin. CLK_ pins are
required to place the
refclk
inputs.
You should place these pins closer to
the UIB_PLL_REF_CLK input, which is
explained below.
hbm_0_example_design_pll_ref_clk_cl
k
LVDS differential input clock used by
the hardened UIB-HBM2 subsystem
You should place this clock on the
UIB_PLL_REF_CLK_00 pins while using
the HBM2 device on the bottom, or the
UIB_PLL_REF_CLK_01 pins while using
the HBM2 on the top.
Jitter Specifications for the Input Reference Clocks
Both the reference clock inputs should meet the following jitter specification: the
refclk
clock source must meet and not exceed the following jitter requirements:
10ps peak to peak, or 1.42ps RMS at 1e-12 BER, 1.22ps at 1e-16 BER.
You can set the frequencies of the reference clocks in the parameter editor, when
generating the HBM2 IP.
Table 13.
Intel Stratix 10 MX HBM2 Supported Frequencies
Intel Stratix 10 MX Device Speed Grade
-1
-2
-3
HBM2 interface maximum
frequency
1000 MHz
800 MHz
600 MHz
User clock maximum
frequency
720 MHz
600 MHz
480 MHz
User clock minimum
frequency
one-quarter of HBM2 interface frequency
Note:
The maximum user clock frequency describes the maximum clock frequency at which
the core <-> UIB interface can run. The actual core clock frequency depends on the
user interface requirements and timing closure in the Intel Quartus Prime Pro Edition
software.
Related Links
•
Intel Stratix 10 MX HBM2 Controller Features
•
Intel Stratix 10 MX HBM2 Controller Details
•
General Parameters for Intel Stratix 10 MX HBM2 IP
•
Intel Stratix 10 MX HBM2 IP Example Design for Synthesis
on page 23
5.2.2 Reset Signals
The HBM2 IP provides three reset inputs.
5 Intel Stratix 10 MX HBM2 IP Interface
UG-20031 | December 2017
Intel
®
Stratix
®
10 MX HBM2 IP User Guide
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