Figure 12.
Example Design Hierarchy
3.7 Intel Stratix 10 MX HBM2 IP Example Design for Synthesis
The top level example design for synthesis is available under
<Design Directory>/
hbm_0_example_design/qii/ed_synth/synth/ed_synth.v
. The
ed_synth_hbm_0_example_design
module is the top-level design module for the
HBM2 IP.
3 Generating the Intel Stratix 10 MX HBM2 IP
UG-20031 | December 2017
Intel
®
Stratix
®
10 MX HBM2 IP User Guide
23
