Intel S875WP1-E Specification Download Page 78

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BIOS Setup Program

S875WP1-E TPS

Revision 4.0

Feature Options

Description

Base I/O address

•

3F8

•

2F8 (default)

•

3E8

•

2E8

This option is displayed only if Serial Port B is set to Enabled.

Specifies the base I/O address for serial port B.

Interrupt

•

IRQ 3 (default)

•

IRQ 4

This option is displayed only if Serial Port B is set to Enabled

Specifies the interrupt for serial port B.

Parallel Port

•

Disabled

•

Enabled

•

Auto (default)

Configures the parallel port.

Auto assigns LPT1 the address 378h and the interrupt IRQ7.

An * (asterisk) displayed next to an address indicates a conflict with
another device.

Mode

•

Output Only

•

Bi-directional
(default)

•

EPP

•

ECP

Selects the mode for the parallel port. Not available if the parallel port
is disabled.

Output Only operates in AT-compatible mode.

Bi-directional operates in PS/2-compatible mode.

EPP is Extended Parallel Port mode, a high-speed
bi-directional mode.

ECP is Enhanced Capabilities Port mode, a high-speed bi-directional
mode.

Base I/O Address

•

378 (default)

•

278

This feature is present only when Parallel Port is set to Enabled

Specifies the base I/O address for the parallel port.

Interrupt

•

IRQ 5

•

IRQ 7 (default)

This feature is present only when Parallel Port is set to Enabled

Specifies the interrupt for the parallel port.

DMA

•

3 (default)

This feature is present only when Parallel Port Mode is set to ECP

Specifies the DMA channel.

10/100 NIC

•

Disabled

•

Enabled
(default)

Enables or disables the on-board LAN#1 device.

Gigabit NIC

•

Disabled

•

Enabled
(default)

Enables or disables the on-board LAN#2 device.

ATI Rage XL Video

•

Disabled

•

Enabled
(default)

Enables or disables the on-board ATI* Rage XL video controller.

Promise PDC20319
S150 TX4

•

Disabled

•

Enabled
(default)

Enables or disables RAID support.

Summary of Contents for S875WP1-E

Page 1: ...Intel Server Board S875WP1 E Technical Product Specification Intel order number C40538 003 Revision 4 0 November 2003 Enterprise Platforms and Services Marketing ...

Page 2: ...lated MTBF numbers and additional notes about ATX12V power supply support November 2003 4 0 Additional notes regarding Serial ATA controller for S875WP1LX sku This product specification applies to the Intel Server Board S875WP1 E with BIOS identifier WP87510A 86B Changes to this specification will be published in the Intel Server Board S875WP1 E Specification Update before being incorporated into ...

Page 3: ...ating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice The S875WP1 E may contain design defects or errors known as errata which may ...

Page 4: ... Firmware Hub FWH 6 3 3 Serial ATA SATA Support 6 3 3 1 SATA Interfaces 6 3 3 2 SATA RAID with ICH5 R Controller 6 3 3 3 SATA RAID with Promise Technology PDC20319 6 3 4 I O Controller 6 3 4 1 Serial Ports 6 3 4 2 Parallel Port 6 3 4 3 Diskette Drive Controller 6 3 4 4 Keyboard and Mouse Interface 6 3 5 Hardware Management Subsystem 6 3 5 1 Hardware Monitoring and Fan Control ASIC 6 3 5 2 Fan Moni...

Page 5: ...locks 6 5 1 Power Connectors 6 5 2 PCI Bus Connectors 6 5 3 AGP Connector 6 5 4 Front Panel Connector 6 5 5 VGA Connector 6 5 6 NIC USB Connector 6 5 7 SATA SATA RAID Connectors 6 5 8 ICH5 R IDE Connectors 6 5 9 Front Panel USB Header 6 5 10 Floppy Connector 6 5 11 Serial Port Connector 6 5 12 Keyboard and Mouse Connector 6 5 13 Miscellaneous Headers 6 5 13 1 Fan Headers 6 5 14 System Recovery and...

Page 6: ...enu 6 7 1 2 Main Menu 6 7 1 3 Advanced Menu 6 7 1 4 Security Menu 6 7 1 5 Power Menu 6 7 1 6 Boot Menu 6 7 1 7 Exit Menu 6 8 Error Reporting and Handling 6 8 1 Error Sources and Types 6 8 1 1 PCI Bus Errors 6 8 1 2 Processor Bus Errors 6 8 1 3 Single Bit ECC Error Throttling Prevention 6 8 1 4 Memory Bus Errors 6 8 2 BIOS Error Messages POST Codes and BIOS Beep Codes 6 8 2 1 BIOS Error Messages 6 ...

Page 7: ... Compatibility Notices 6 9 4 1 FCC USA 6 9 4 2 INDUSTRY CANADA ICES 003 6 9 4 3 Europe CE Declaration of Conformity 6 9 4 4 Taiwan Declaration of Conformity 6 9 4 5 Korean RRL Compliance 6 9 4 6 Australia New Zealand 6 9 5 Replacing the Back Up Battery 6 9 6 Calculated Mean Time Between Failures MTBF 6 9 7 Mechanical Specifications 6 Glossary VI ...

Page 8: ...c Mode 6 Figure 4 Examples of Single Channel Configuration with Dynamic Mode 6 Figure 5 Examples of Single Channel Configuration without Dynamic Mode 6 Figure 6 Intel 875P Chipset Block Diagram 6 Figure 7 USB Port Configuration 6 Figure 8 Location of the Standby Power Indicator LED CR7J1 6 Figure 9 LAN Connector LED Locations 6 Figure 10 S875WP1 E Server Board Mechanical Drawing 6 Figure 11 Intel ...

Page 9: ...000 LAN Connector LED States 6 Table 14 System Memory Map 6 Table 15 I O Map 6 Table 16 DMA Channels 6 Table 17 PCI Configuration Space Map 6 Table 18 Interrupts 6 Table 19 PCI Interrupt Routing Map 6 Table 20 Power Connector Pin out J2J2 6 Table 21 12V CPU Power Connector J4C1 6 Table 22 Auxiliary Power Connector J4J1 6 Table 23 PCI Bus Connectors 6 Table 24 AGP Connector 6 Table 25 High Density ...

Page 10: ... Boot Configuration Submenu 6 Table 47 Peripheral Configuration Submenu 6 Table 48 Drive Configuration Submenu 6 Table 49 Primary Secondary Master Slave Submenus 6 Table 50 Floppy Configuration Submenu 6 Table 51 Event Log Configuration Submenu 6 Table 52 Video Configuration Submenu 6 Table 53 USB Configuration Submenu 6 Table 54 Chipset Configuration Submenu 6 Table 55 Fan Control Configuration S...

Page 11: ... Recovery Code Checkpoints 6 Table 70 Runtime Code Uncompressed in F000 Shadow RAM 6 Table 71 BIOS Beep Codes 6 Table 72 Bus Initialization Checkpoints 6 Table 73 Upper Nibble High Byte Functions 6 Table 74 Lower Nibble High Byte Functions 6 Table 75 Absolute Maximum Ratings 6 Table 76 S875WP1 E Power Budget 6 ...

Page 12: ...List of Tables S875WP1 E TPS Revision 4 0 xii This page intentionally left blank ...

Page 13: ...rd S875WP1 E which includes product codes S875WP1 and S875WP1LX When appropriate the specific product code is used to relay information that pertains only to a specific version of the Intel Server Board S875WP1 E This document is divided into the following main categories Chapter 2 Server Board Overview Chapter 3 Functional Architecture Chapter 4 Technical Reference Chapter 5 Connectors and Jumper...

Page 14: ...uency when using an Intel Pentium 4 processor with 800 MHz system bus frequency PC2100 266 MHZ PC2100 266 MHZ memory may only be used with an Intel Pentium 4 processor with 400 MHz or 533 MHz system bus frequency only One AGP bus with AGP connector supporting 1 5 V and 0 8V AGP cards at 4X and 8X One independent PCI bus 32 bit 33 MHz 5 V with three PCI connectors and two embedded devices Integrate...

Page 15: ...ture SSI compliant connectors for SSI interface support front panel power connector Hardware Monitor Subsystem Voltage sense to detect out of range power supply voltages Thermal sense to detect out of range thermal values Four fan sense inputs used to monitor fan activity ...

Page 16: ...ary IDE Connector K Serial B Header L System Fan 1 Header M System Fan 2 Header N Front Panel Connector O BIOS Configuration Jumper J8J2 P SCSI LED Header Q Hot Swap Backplane Header R Battery S SATA A1 through SATA A4 Connector S875WP1LX only slots numbered from left to right T Chassis Intrusion Header U PCI 32 33 Slots 1 3 slots numbered from top to bottom V System Fan 3 Header W Front Panel USB...

Page 17: ... Technology 2 40 2 60 2 80 and 3 0 GHz 800 MHz 512 KB Pentium 4 processor with Hyperthreading Technology 3 06 GHz 533 MHz 512 KB Pentium 4 processor 2 0 2 26 2 4 2 53 2 6 2 66 and 2 8 GHz 400 533 MHz 512 KB CAUTION Use only the processors listed above Use of unsupported processors can damage the board the processor and the power supply See the Intel Server Board S875WP1 E Specification Update or g...

Page 18: ... two row DIMMs Table 2 Supported Memory Configurations DIMM Capacity Configuration DDR SDRAM Density DDR SDRAM Organization Front side Back side Number of DDR SDRAM Devices 64 MB SS 64 Mbit 8 M x 8 empty 8 64 MB SS 128 Mbit 8 M x 16 empty 4 128 MB DS 64 Mbit 8 M x 8 8 M x 8 16 128 MB SS 128 Mbit 16 M x 8 empty 8 128 MB SS 256 Mbit 16 M x 16 empty 4 256 MB DS 128 Mbit 16 M x 8 16 M x 8 16 256 MB SS...

Page 19: ...ing or upgrading memory to avoid interference with the memory retention mechanism To be fully compliant with all applicable DDR SDRAM memory specifications the board should be populated with DIMMs that support the Serial Presence Detect SPD data structure This allows the BIOS to read the SPD data and program the chipset to accurately configure memory settings for optimum performance If non SPD mem...

Page 20: ...aracteristics Highest Dual Channel with Dynamic Mode All DIMMs matched Example configurations are shown in Figure 2 Dual Channel without Dynamic Mode DIMMs matched from Channel A to Channel B DIMMs not matched within channels Example configuration is shown in Figure 3 Single Channel with Dynamic Mode Single DIMM or DIMMs matched with a channel Example configurations are shown in Figure 4 Lowest Si...

Page 21: ...annel B DIMM 0 Channel A DIMM 1 Channel B DIMM 1 Dual Channel Configuration with Dynamic Mode All DIMMs matched OM15978 Intel 82875P MCH Channel A DIMM 0 Channel B DIMM 0 Channel A DIMM 1 Channel B DIMM 1 Example 2 Example 1 Figure 2 Examples of Dual Channel Configuration with Dynamic Mode ...

Page 22: ...5P MCH Channel A DIMM 0 Channel B DIMM 0 Channel A DIMM 1 Channel B DIMM 1 Dual Channel Configuration without Dynamic Mode DIMMs not matched within channel DIMMs match Channel A to Channel B OM15979 Figure 3 Example of Dual Channel Configuration without Dynamic Mode ...

Page 23: ... Channel A DIMM 1 Channel B DIMM 1 Single Channel Configuration with Dynamic Mode Single DIMM or DIMMs matched within Channel OM15980 Intel 82875P MCH Channel A DIMM 0 Channel B DIMM 0 Channel A DIMM 1 Channel B DIMM 1 Example 2 Example 1 Figure 4 Examples of Single Channel Configuration with Dynamic Mode ...

Page 24: ...l B DIMM 0 Channel A DIMM 1 Channel B DIMM 1 Single Channel Configuration without Dynamic Mode DIMMs not matched OM15981 Intel 82875P MCH Channel A DIMM 0 Channel B DIMM 0 Channel A DIMM 1 Channel B DIMM 1 Example 2 Example 1 Figure 5 Examples of Single Channel Configuration without Dynamic Mode ...

Page 25: ...b Architecture interface The ICH5 R is a centralized controller for the Server Board S875WP1 E s I O paths The FWH provides the nonvolatile storage of the BIOS The component combination provides the chipset interfaces as shown in Figure 6 875P Chipset 82801ER I O Controller Hub ICH5 R 82875P Memory Controller Hub MCH 82802AC 8 Mbit Firmware Hub FWH AHA Bus System Bus UDMA 33 ATA 66 100 USB AGP Int...

Page 26: ...on is not supported Install memory in the DIMM sockets prior to installing the AGP video card to avoid interference with the memory retention mechanism The AGP connector is keyed for Universal 0 8 V AGP 3 0 cards or 1 5 V AGP 2 0 cards only Do not attempt to install a legacy 3 3 V AGP card The AGP connector is not mechanically compatible with legacy 3 3 V AGP cards For information about Refer to T...

Page 27: ...ation about Refer to The location of the USB connectors on the back panel Figure 1 The location of the front panel USB connector Figure 1 The signal names of the front panel USB header Section 5 9 Legacy USB support Section 6 4 Wake from USB Section 3 6 3 2 3 IDE Interfaces The ICH5 R IDE controller has two independent bus mastering IDE interfaces that can be independently enabled The IDE interfac...

Page 28: ...an LS 120 drive as an ATAPI floppy drive To ensure correct operation do not configure the drive as a hard disk drive For information about Refer to The location of the IDE connectors Figure 1 The signal names of the IDE connectors Table 30 BIOS Setup program s Boot Configuration menu Section 7 1 3 2 Drive Configuration Submenu Section 7 1 3 4 3 2 3 1 SCSI Hard Drive Activity LED Connector The SCSI...

Page 29: ...timated life of three years When the computer is plugged in the standby current from the power supply extends the life of the battery The clock is accurate to 13 minutes year at 25 ºC with 3 3 VSB applied The time date and CMOS values can be specified in the BIOS Setup program The CMOS values can be returned to their defaults by using the BIOS Setup program NOTE If the battery and AC power fail cu...

Page 30: ...erate in both legacy and native modes In legacy mode standard IDE I O and IRQ resources are assigned IRQ 14 and 15 In native mode standard PCI resource steering is used Native mode is the preferred mode for configurations using the Windows XP and Windows 2000 operating systems Key features include Two SATA ports Maximum throughput of 150MB s Smaller cable NOTE Many SATA drives use new low voltage ...

Page 31: ...gement 1 1 Support 48 bit LBA format for drives larger than 128GB 32 bit 33 MHz bus speed and 150 MB sec sustained transfer rate The Promise PDC20319 supports SATA RAID through four SATA Channels The RAID Engine supports advance chained packet commands for XOR and four independent ATA operations improving performance for all RAID levels In a RAID configuration multiple SATA hard drives are placed ...

Page 32: ...ation options for the I O controller For information about Refer to SMSC LPC47M172 I O controller http www smsc com 3 4 1 Serial Ports The Intel Server Board S875WP1 E has one 9 pin D sub serial port connector and one 2 x 5 serial port header The serial port A connector is located in the rear I O area The serial port B header is located near the main power connector The serial ports NS16C550 compa...

Page 33: ...rted diskette drive capacities and sizes Table 50 3 4 4 Keyboard and Mouse Interface PS 2 keyboard and mouse connectors are located on the back panel The 5 V lines to these connectors are protected with a PolySwitch fuse circuit that like a self healing fuse reestablishes the connection after an overcurrent condition is removed NOTE The keyboard is supported in the bottom PS 2 connector and the mo...

Page 34: ...al ambient temperature sensor 7 Two remote thermal diode sensors for direct monitoring of processor temperature and ambient temperature sensing 8 Power supply monitoring of five voltages 5 V 12 V 3 3 V Standby 1 5 V and VCCP to detect levels above or below acceptable values 9 Thermally monitored closed loop fan control for four fans that can adjust the fan speed or switch the fans on or off as nee...

Page 35: ...Configuration and Power Interface ACPI 11 Hardware support Power connector Fan connectors LAN wake capabilities Instantly Available PC technology Wake from USB Wake from PS 2 devices Power Management Event PME wake up support 3 6 1 Advanced Configuration and Power Interface ACPI ACPI gives the operating system direct control over the power management and Plug and Play functions of a computer The u...

Page 36: ...ates based on user preferences and knowledge of how devices are being used by applications Devices that are not being used can be turned off The operating system uses information from applications and user settings to put the system as a whole into a low power state Table 6 lists the power states supported by the Server Board S875WP1 E along with the associated system power targets See the ACPI sp...

Page 37: ...r from specific states Table 7 Wake up Devices and Events These devices events can wake up the computer from this state LAN S1 S3 S4 S5 Note Modem back panel Serial Port A S1 S3 PME S1 S3 S4 S5 Note Power switch S1 S3 S4 S5 PS 2 devices S1 S3 RTC alarm S1 S3 S4 S5 USB S1 S3 NOTE For LAN and PME S5 is disabled by default in the BIOS Setup program Setting this option to Power On will enable a wake u...

Page 38: ...power from the 5 V standby line The sections discussing these features describe the incremental standby power requirements for each 3 6 2 1 Power Connector ATX12V or EPS12V compliant power supplies and the Intel Server Board S875WP1 E can turn off the system power through software control When the system receives the correct command from the operating system the power supply removes non standby vo...

Page 39: ...f or in the S3 S4 or S5 state Wired to a fan tachometer input of the hardware monitoring and fan control ASIC Closed loop fan control that can adjust the fan speed or switch the fan on or off as needed For information about Refer to The location of the fan connectors Figure 1 The signal names of the fan connectors Section 5 13 1 3 6 2 3 LAN Wake Capabilities CAUTION For LAN wake capabilities the 5...

Page 40: ...eturns to its last known wake state Table 7 lists the devices and events that can wake the computer from the S3 state The server board supports the PCI Bus Power Management Interface Specification Add in boards that also support this specification can participate in power management and can be used to wake the computer The use of Instantly Available PC technology requires operating system support ...

Page 41: ...the computer from an ACPI S1 or S3 state NOTE Wake from USB requires the use of a USB peripheral that supports it 3 6 3 2 Wake from PS 2 Devices PS 2 device activity wakes the computer from an ACPI S1 or S3 state 3 6 3 3 PME Wake up Support When the PME signal on the PCI bus is asserted the computer wakes from an ACPI S1 S3 S4 or S5 state with Wake on PME enabled in BIOS ...

Page 42: ...cessor MCH Memory DIMMs and the ITP 28 66 MHz clock for MCH and the AGP clocks 29 48 MHz clock for USB 30 33 3 MHz PCI reference clock 14 318 MHz ICH5 R and Super I O clocks The S875WP1 E baseboard also provides asynchronous clock generators 31 25 MHz clocks for the embedded network interface controllers 32 29 498928 MHz clock for the embedded video controller 33 20 MHz clock for the Promise PDC20...

Page 43: ... connector 17 PCI slot 2 middle slot 18 PCI slot 3 closest to left edge of board 22 ATI Rage XL Video Controller 23 ATA 100 controller Promise Technology PDC20319 3 8 2 Video Controller The Intel Server Board S875WP1 E provides an ATI Rage XL PCI graphics accelerator along with 8 MB of video SDRAM and support circuitry for an embedded SVGA video subsystem The ATI Rage XL chip contains a SVGA video...

Page 44: ...ed Supported Supported 1024x768 60 72 75 90 100 Supported Supported Supported Supported 1280x1024 43 60 70 72 Supported Supported 1600x1200 60 66 76 85 Supported 3D Mode Refresh Rate Hz S875WP1 E 3D Video Mode Support with Z Buffer Disabled 640x480 60 72 75 90 100 Supported Supported Supported Supported 800x600 60 70 75 90 100 Supported Supported Supported Supported 1024x768 60 72 75 90 100 Suppor...

Page 45: ...ollowing features 38 Integrated IEEE 802 3 10Base T and 100Base TX compatible PHY 39 IEEE 802 3u auto negotiation support 40 Full duplex support at both 10 Mbps and 100 Mbps operation 41 Low power 3 3 V device with reduced power in unplugged mode and automatic detection of unplugged mode 3 port LED support The 82547EI is controlled by the CSA interface off of the MCH and supports the following fea...

Page 46: ...ate Indicates Off 10 Mbit sec data rate is selected Green left LED On 100 Mbit sec data rate is selected Off LAN link is not established On steady state LAN link is established Yellow right LED On brighter and pulsing The computer is communicating with another computer on the LAN Table 13 describes the LED states when the board is powered up and the 10 100 1000 Mbits sec LAN subsystem is operating...

Page 47: ...IOS 639 K 640 K 9FC00 9FFFF 1 KB Extended BIOS data movable by memory manager software 512 K 639 K 80000 9FBFF 127 KB Extended conventional memory 0 K 512 K 00000 7FFFF 512 KB Conventional memory 4 2 I O Map Table 15 I O Map Address hex Size Description 0000 00FF 256 bytes Used by the Server Board S875WP1 E Refer to the ICH5 R data sheet for dynamic addressing information 0170 0177 8 bytes Seconda...

Page 48: ...ter 0CFC 0CFF 4 bytes PCI configuration data register FFA0 FFA7 8 bytes Primary bus master IDE registers FFA8 FFAF 8 bytes Secondary bus master IDE registers Notes 1 Default but can be changed to another address range 2 Dword access only 3 Byte access only 4 3 DMA Channels Table 16 DMA Channels DMA Channel Number Data Width System Resource 0 8 or 16 bits Open 1 8 or 16 bits Parallel port 2 8 or 16...

Page 49: ...e 00 1F 00 Intel 82801ER ICH5 R PCI to LPC bridge 00 1F 01 IDE controller 00 1F 03 SMBus controller 00 1F 05 AC 97 audio controller 00 1F 06 AC 97 modem controller optional 00 1D 00 USB UHCI controller 1 00 1D 01 USB UHCI controller 2 00 1D 02 USB UHCI controller 3 00 1D 07 EHCI controller 01 00 00 AGP add in card 02 08 00 LAN controller 02 00 00 PCI bus connector 1 02 01 00 PCI bus connector 2 02...

Page 50: ...d Play option User available 6 Diskette drive 7 LPT1 Note 1 8 Real time clock 9 Reserved for ICH5 R system management bus 10 User available 11 User available 12 Onboard mouse port if present else user available 13 Reserved math coprocessor 14 Primary IDE if present else user available 15 Secondary IDE if present else user available 16 USB UHCI controller 1 through PIRQA 17 User available through P...

Page 51: ...CH5 R has eight programmable interrupt request PIRQ input signals All PCI interrupt sources either onboard or from a PCI add in card connect to one of these PIRQ signals Some PCI interrupt sources are electrically tied together on the Server Board S875WP1 E and therefore share the same interrupt Table 19 shows an example of how the PIRQ signals are routed For example using Table 19 as a reference ...

Page 52: ...al Color Pin Signal Color 1 3 3Vdc Orange 13 3 3Vdc Orange 2 3 3Vdc Orange 14 12Vdc Blue 3 COM Black 15 COM Black 4 5Vdc Red 16 PS_ON Green 5 COM Black 17 COM Black 6 5Vdc Red 18 COM Black 7 COM Black 19 COM Black 8 PWR_OK Gray 20 RSVD_ 5V White 9 5VSB Purple 21 5Vdc Red 10 12Vdc Yellow 22 5Vdc Red 11 12Vdc Yellow 23 5Vdc Red 12 3 3Vdc Orange 24 COM Black Table 21 12V CPU Power Connector J4C1 Pin ...

Page 53: ...round B37 DEVSEL A7 INTC B7 INTB A38 STOP B38 Ground A8 5 V B8 INTD A39 3 3 V B39 LOCK A9 2 Reserved B9 Not connected PRSNT1 See Note A40 SMBus Clock Line B40 PERR A10 5 V I O B10 Reserved 3 A41 SMBus Data Line B41 3 3 V A11 Reserved B11 Not connected PRSNT2 See Note A42 Ground B42 SERR A12 Ground B12 Ground A43 PAR B43 3 3 V A13 Ground B13 Ground A44 AD15 B44 C BE1 A14 3 3 V aux B14 Reserved 4 A4...

Page 54: ...1 12 V B1 Not connected A34 Vddq B34 Vddq A2 TYPEDET B2 5 V A35 AD22 B35 AD21 A3 Reserved B3 5 V A36 AD20 B36 AD19 A4 Not connected B4 Not connected A37 Ground B37 Ground A5 Ground B5 Ground A38 AD18 B38 AD17 A6 INTA B6 INTB A39 AD16 B39 C BE2 A7 RST B7 CLK A40 Vddq B40 Vddq A8 GNT1 B8 REQ A41 FRAME B41 IRDY A9 Vcc3 3 B9 Vcc3 3 A42 Reserved B42 3 3 V aux A10 ST1 B10 ST0 A43 Ground B43 Ground A11 R...

Page 55: ...acy 3 3 V AGP cards 5 4 Front Panel Connector A high density 34 pin SSI header is provided to support a system front panel The header contains reset NMI power control buttons and LED indicators The following table details the pin out of the header Table 25 High Density Front Panel 34 Pin Header Pin Out J7J1 Pin Signal Name Pin s Function 1 Power LED Anode 2 5VSB 3 Key 4 Unused 5 GND 6 Unused 7 HDD...

Page 56: ...l sync 15 V_MONID2 5 6 NIC USB Connector The Intel Server Board S875WP1 E supports two Magjack3 connectors dual USB RJ45 The following table details the pin out of the connector Table 27 Magjack3 Connector dual USB RJ45 Gbe Pin Out JA4A1 Pin Signal Name Pin Signal Name 1 VREG_USB_BP_RIGHT 16 LAN_MDI_3 2 USB_BACK1_R 17 LAN_MDI_3 3 USB_BACK1_R 18 GND 4 GND 19 LAN_LINK_UP 5 VREG_USB_BP_RIGHT 20 LAN_A...

Page 57: ... LAN_LILED 7 USB_BACK6_R 22 LAN_ACT_LED 8 GND 23 GND 9 NC 24 GND 10 LAN_TDP 25 GND 11 LAN_TDN 26 GND 12 LAN_RDP 27 GND 13 LAN_RDN 28 GND 14 NC 29 GND 15 NC 30 GND 5 7 SATA SATA RAID Connectors The S875WP1 E board provides two S875WP1 or six S875WP1LX SATA SATA RAID connectors The pin out for all connectors is identical and is listed in the following table Table 29 SATA 7 pin Connectors Pin Out J9E...

Page 58: ...nd 23 I O Write 24 Ground 25 I O Read 26 Ground 27 IOCHRDY 28 Ground 29 DDACK0 DDACK1 30 Ground 31 IRQ 14 IRQ 15 32 Not connected 33 PDA1 Address 1 34 GPIO_DMA66_Detect_Pri GPIO_DMA66_Detect_Sec 35 PDA0 Address 0 36 PDA2 Address 2 37 Chip Select 1P Chip Select 1S 38 Chip Select 3P Chip Select 3S 39 Activity 40 Ground 5 9 Front Panel USB Header A header on the server board provides an option to sup...

Page 59: ...R Stepper Motor Direction 19 GND 20 STEP Step Pulse 21 GND 22 WDATA Write Data 23 GND 24 WGATE Write Enable 25 GND 26 TRK0 Track 0 27 NC 28 WRTPRT Write Protect 29 GND 30 RDATA Read Data 31 GND 32 HDSEL Side 1 Select 33 GND 34 DSKCHG Diskette Change 5 11 Serial Port Connector The Intel Server Board S875WP1 E has one 9 pin D sub serial port connector and one 2 x 5 serial port connector The followin...

Page 60: ...circuit that like a self healing fuse reestablishes the connection after an overcurrent condition is removed NOTE The keyboard is supported in the bottom PS 2 connector and the mouse is supported in the top PS 2 connector Power to the computer should be turned off before a keyboard or mouse is connected or disconnected The keyboard controller contains the AMI keyboard and mouse controller code pro...

Page 61: ...5 14 System Recovery and Update Jumper CAUTION Do not move any jumpers with the power on Always turn off the power and unplug the power cord from the computer before changing a jumper setting Otherwise the board could be damaged This 3 pin jumper block determines the BIOS Setup program mode Table 37 describes the jumper settings for the three modes normal configure and recovery When the jumper is ...

Page 62: ...om the computer before changing a jumper setting Otherwise the board could be damaged This 3 pin jumper block allows the user to clear CMOS Table 38 describes the jumper settings for the two modes normal and clear CMOS When the jumper is set to Clear CMOS mode and the computer is powered up the contents of the CMOS are cleared Table 38 Clear CMOS Jumper Settings J8G1 Function Mode Jumper Setting C...

Page 63: ...microcode version in the BIOS and reports if the two match For information about Refer to The Intel Server Board S875WP1 E s compliance level with Plug and Play Section 3 6 1 3 6 1 BIOS Flash Memory Organization The Intel 82802AC Firmware Hub FWH includes an 8 megabit symmetrical flash memory device Internally the device is grouped into eight 64 KB blocks that are individually erasable lockable an...

Page 64: ...rotocols If an ATA 66 100 disk drive and a disk drive using any other IDE transfer protocol are attached to the same cable the maximum transfer rate between the drives is reduced to that of the slowest device Do not connect an ATA device as a slave on the same IDE cable as an ATAPI master device For example do not connect an ATA hard drive as a slave to an ATAPI CD ROM drive 6 3 System Management ...

Page 65: ... the computer legacy support is disabled 2 POST begins 3 Legacy USB support is enabled by the BIOS allowing the user to use a USB keyboard to enter and configure the BIOS Setup program and the maintenance menu 4 POST completes 5 The operating system loads While the operating system is loading USB keyboard and mice are recognized and may be used to configure the operating system Keyboard and mice a...

Page 66: ...the main BIOS This process is fault tolerant to prevent boot block corruption 65 Updating the BIOS boot block separately 66 Changing the language section of the BIOS 67 Updating replaceable BIOS modules such as the video BIOS module Inserting a custom splash screen NOTE Review the instructions distributed with the upgrade utility before attempting a BIOS update 6 5 1 Language Support The BIOS Setu...

Page 67: ...e Intel World Wide Web site NOTE Even if the computer is configured to boot from an LS 120 diskette in the Setup program s Removable Devices submenu the BIOS recovery diskette must be a standard 1 44 MB diskette not a 120 MB diskette For information about Refer to The BIOS recovery mode jumper settings Section 5 14 The Boot Device Priority menu in the BIOS Setup program Section 7 1 6 1 6 7 Boot Op...

Page 68: ...7 2 Booting Without Attached Devices For use in embedded applications the BIOS has been designed so that after passing the POST the operating system loader is invoked even if the following devices are not present 68 Video adapter 69 Keyboard Mouse ...

Page 69: ... be seen Monitors and hard disk drives with minimum initialization times can also contribute to a boot time that might be so fast that necessary logo screens and POST messages cannot be seen This boot time may be so fast that some drives might be not be initialized at all If this condition should occur it is possible to introduce a programmable delay ranging from three to 30 seconds using the Hard...

Page 70: ...e computer Table 39 shows the effects of setting the supervisor password and user password This table is for reference only and is not displayed on the screen Table 39 Supervisor and User Password Functions Password Set Supervisor Mode User Mode Setup Options Password to Enter Setup Password During Boot Neither Can change all options Note Can change all options See Note None None None Supervisor o...

Page 71: ...ipset Sets passwords and security features Configures power management features Selects boot options and power supply controls Saves or discards changes to Setup program options NOTE In this chapter all examples of the BIOS Setup program menu bar include the maintenance menu however the maintenance menu is displayed only when the board is in configuration mode Section 5 14 shows how to put the boa...

Page 72: ...nagement Boot Integrity Service BIS credentials CPU Stepping Signature No options Displays CPU s Stepping Signature CPU Microcode Update Revision No options Displays CPU s Microcode Update Revision 7 1 2 Main Menu To access this menu select Main on the menu bar at the top of the screen Maintenance Main Advanced Security Power Boot Exit Table 43 describes the Main Menu This menu reports processor a...

Page 73: ...nstalled memory supported ECC If non ECC memory is installed BIOS will detect and change the setting to non ECC Language English default Español Selects the current default language used by the BIOS Deutsch Italiano and Français available via lng files System Time Hour minute and second Set current time Use the Tab key to navigate fields System Date Day of week Month day year Set current date Use ...

Page 74: ...nu Displays the Boot Configuration submenu Peripheral Configuration Select to display submenu Displays the Peripheral Configuration submenu Drive Configuration Select to display submenu Displays the Drive Configuration submenu Floppy Configuration Select to display submenu Displays the Floppy Configuration submenu Event Log Configuration Select to display submenu Displays the Event Log Configurati...

Page 75: ...trol Configuration Hardware Monitoring Remote Access Configuration The submenu represented by Table 45 is for configuring the IRQ priority of PCI slots individually Table 45 PCI Configuration Submenu Feature Options Description PCI Slot 1 IRQ Priority Auto default 5 9 10 11 Allows selection of IRQ priority PCI Slot 2 IRQ Priority Note 1 Auto default 5 9 10 11 Allows selection of IRQ priority PCI S...

Page 76: ...guration The submenu represented by Table 46 is for setting Plug and Play PnP options resetting configuration data and the power on state of the Numlock key Table 46 Boot Configuration Submenu Feature Options Description Plug and Play O S No default Yes Specifies if manual configuration is desired No lets the BIOS configure all devices This setting is appropriate when using a Plug and Play operati...

Page 77: ...Auto default Configures serial port A Auto assigns the first free COM port normally COM1 the address 3F8h and the interrupt IRQ4 An asterisk displayed next to an address indicates a conflict with another device Base I O Address 3F8 default 2F8 3E8 2E8 This option is available only when Serial Port A is set to Enabled Specifies the base I O address for serial port A Interrupt IRQ 3 IRQ 4 default Th...

Page 78: ...le mode Bi directional operates in PS 2 compatible mode EPP is Extended Parallel Port mode a high speed bi directional mode ECP is Enhanced Capabilities Port mode a high speed bi directional mode Base I O Address 378 default 278 This feature is present only when Parallel Port is set to Enabled Specifies the base I O address for the parallel port Interrupt IRQ 5 IRQ 7 default This feature is presen...

Page 79: ...ring Remote Access Configuration The menu represented in Table 48 is used to configure drive device options Table 48 Drive Configuration Submenu Feature Options Description ATA Drive Configuration Disabled Legacy Enhanced default Selects the mode for the integrated IDE controller When Legacy is selected a maximum of 4 drives can be installed When Enhanced is selected a maximum of 6 drives can be i...

Page 80: ... Slave submenu PATA Secondary Master Select to display sub menu Reports type of connected IDE device When selected displays the Secondary IDE Master submenu PATA Secondary Slave Select to display sub menu Reports type of connected IDE device When selected displays the Secondary IDE Slave submenu 7 1 3 4 1 Primary Secondary Third Fourth Master Slave Submenus To access these submenus select Advanced...

Page 81: ...is selected as the type PIO Mode Auto default 0 1 2 3 4 This option can be changed only if User is selected as the type DMA Mode Auto default SWDMA 0 1 or 2 MWDMA 0 1 or 2 UDMA 0 1 2 3 4 5 This option can be changed only if User is selected as the type SWDMA Single Word DMA MWDMA Multi Word DMA UDMA Ultra DMA Feature Options Description S M A R T Auto default Disabled Enabled This option can be ch...

Page 82: ...figuration Fan Control Configuration Hardware Monitoring Remote Access Configuration The submenu represented by Table 50 is used for configuring the diskette drive Table 50 Floppy Configuration Submenu Feature Options Description Diskette Controller Disabled Enabled default Disables or enables the integrated diskette controller Floppy A Disabled 360 KB 5 inch 1 2 MB 5 inch 720 KB 3 inch 1 44 MB 3 ...

Page 83: ...Control Configuration Hardware Monitoring Remote Access Configuration The submenu represented by Table 51 is used to configure the event logging features Table 51 Event Log Configuration Submenu Feature Options Description Event Log No options Indicates if there is space available in the event log View Event Log Enter Displays the event log Clear Event Log OK default Cancel Clears the event log af...

Page 84: ...ipset Configuration Fan Control Configuration Hardware Monitoring Remote Access Configuration The submenu represented by Table 52 is used to configure the video features Table 52 Video Configuration Submenu Feature Options Description AGP Aperture Size 4MB 8MB 16MB 32MB 64MB default 128MB 256MB Sets the aperture size for the AGP video controller Primary Video Adapter AGP PCI default Allows selecti...

Page 85: ...pset Configuration Fan Control Configuration Hardware Monitoring Remote Access Configuration The submenu represented by Table 52 is used to configure the USB features Table 53 USB Configuration Submenu Feature Options Description High Speed USB Enabled default Disabled Enables or disables the USB 2 0 driver Disable this option if the driver is not available Legacy USB support Disabled Enabled defa...

Page 86: ...Control Configuration Hardware Monitoring Remote Access Configuration The submenu represented by Table 52 is used to configure the chipset features Table 54 Chipset Configuration Submenu Feature Options Description ISA Enable Bit Disabled Enabled default This option is required by some IDE expansion devices PCI Latency Timer 32 64 96 128 160 192 224 248 Extended Configuration Default default User ...

Page 87: ...mmed according to the memory detected Manual Aggressive Selects the most aggressive user defined timings Manual User Defined Allows manual override of detected SDRAM settings CPC Override Auto default Enable Disable Command Per Clock When enabled it allows the DRAM controller to attempt chip select assertions in two consecutive common clocks SDRAM RAS Act To Pre No options SDRAM CAS Latency No opt...

Page 88: ...eo Configuration USB Configuration Chipset Configuration Fan Control Configuration Hardware Monitoring Remote Access Configuration The submenu represented by Table 52 is used to configure the fan control features Table 55 Fan Control Configuration Submenu Feature Options Description Fan Control Disabled Enabled default Lowest Fan Speed Slow default Off This option is available only if Enabled is s...

Page 89: ...onitored These options can be viewed only not changed Table 56 Hardware Monitoring Submenu Feature Options Description Processor Zone Temperature No options Displays processor zone temperature System Zone 1 Temperature No options Displays system zone 1 temperature System Zone 2 Temperature No options Displays system zone 2 temperature Processor Fan Speed No options Displays the speed at which the ...

Page 90: ...nies the ability to remotely manage the system Serial Port Number COM1 default COM2 This option is available only if Enabled is set for the Remote Access option Specifies the serial port to use for console redirection In addition to selecting the port number in BIOS setup make sure the selected port is enabled for use Serial Port Mode 115200 8 n 1 57600 8 n 1 default 19200 8 n 1 This option is ava...

Page 91: ...assword can be up to seven alphanumeric characters Specifies the user password Clear User Password Note 1 Ok default No Clears the user password User Access Level Note 2 No Access View Only Limited Full default Sets BIOS Setup Utility access rights for user level No Access User cannot access BIOS Setup View Only User can view BIOS Setup but cannot make any changes Limited User can make limited cha...

Page 92: ... to the server Stay Off keeps the power off until the power button is pressed Last State restores the previous power state before power loss occurred Wake on PCI PME Stay Off default Power On Specifies how the computer responds to a PCI power management event 7 1 5 1 ACPI Submenu To access this menu select Power on the menu bar then ACPI Maintenance Main Advanced Security Power Boot Exit ACPI The ...

Page 93: ...IOS Boot Disabled Enabled default Enables the computer to boot without running certain POST tests Scan User Flash Area Disabled Enabled default Enables the BIOS to scan the flash memory for user binary files that are executed at boot time PXE Boot to LAN Disabled default Enabled Enables PXE boot USB Boot Disabled Enabled default Enables the computer to boot from USB boot devices Boot Device Priori...

Page 94: ...devices priority Table 62 Boot Device Priority Submenu Feature Options Description 1st Boot Device 2nd Boot Device 3 rd Boot Device 4 th Boot Device Note 1 Removable Dev Hard Drive ATAPI CD ROM Intel UNDI PXE Disabled Specifies the boot sequence from the available types of boot devices To specify boot sequence 1 Select the boot device with or 2 Press Enter to set the selection as the intended boot...

Page 95: ...isk drive priority Table 63 Hard Disk Drives Submenu Feature Options Description 1st Hard Disk Drive Note Dependent on installed hard drives Specifies the boot sequence from the available hard disk drives To specify boot sequence 1 Select the boot device with or 2 Press Enter to set the selection as the intended boot device Note This boot device submenu appears only if at least one boot device of ...

Page 96: ...device priority Table 64 Removable Devices Submenu Feature Options Description 1st Removable Device Note Dependent on installed removable devices Specifies the boot sequence from the available removable devices To specify boot sequence 1 Select the boot device with or 2 Press Enter to set the selection as the intended boot device Note This boot device submenu appears only if at least one boot devi...

Page 97: ...es the maximum number of ATAPI CDROM drives supported by the BIOS 7 1 7 Exit Menu To access this menu select Exit from the menu bar at the top of the screen Maintenance Main Advanced Security Power Boot Exit The menu represented in Table 66 is for exiting the BIOS Setup program saving changes and loading and saving defaults Table 66 Exit Menu Feature Description Exit Saving Changes Exits and saves...

Page 98: ...ors On the S875WP1 E platform the Heceta chip manages general hardware monitoring sensors on a hardware level however action is only taken by software i e an application such as LANDesk Client Manager 8 1 1 PCI Bus Errors The PCI bus defines two error pins PERR and SERR for reporting PCI parity errors and system errors respectively In the case of PERR the PCI bus master has the option to retry the...

Page 99: ...ious hardware problem that must be repaired at the earliest possible time The system BIOS implements this feature for correctable bus errors If ten errors occur within 30 minutes the corresponding error handler disables further reporting of that type of error The BIOS re enables logging and SMIs the next time the system is rebooted 8 1 4 Memory Bus Errors The MCH is programmed to flag and log sing...

Page 100: ... different than what has been stored in CMOS Check Setup to make sure type is correct CMOS Checksum Bad The CMOS checksum is incorrect CMOS memory may have been corrupted Run Setup to reset values CMOS Settings Wrong CMOS values are not the same as the last boot These values have either been corrupted or the battery has failed CMOS Date Time Not Set The time and or date values stored in CMOS are i...

Page 101: ...uch as a seven segment display The tables below offer descriptions of the POST codes generated by the BIOS Table 68 defines the uncompressed INIT code checkpoints Table 69 describes the boot block recovery code checkpoints and Table 70 lists the runtime code uncompressed in F000 shadow RAM Some codes are repeated in the tables because that code applies to more than one operation Table 68 Uncompres...

Page 102: ...tion to be done next 0B Any initialization before keyboard BAT to be done next 0C KB controller I B free To issue the BAT command to keyboard controller 0E Any initialization after KB controller BAT to be done next 0F Keyboard command byte to be written 10 Going to issue Pin 23 24 blocking unblocking command 11 Going to check pressing of INS END key during power on 12 To init CMOS if Init CMOS in ...

Page 103: ...below 1M cleared SOFT RESET Going to clear memory above 1M 4D Memory above 1M cleared SOFT RESET Going to save the memory size Go to check point 52h 4E Memory test started NOT SOFT RESET About to display the first 64k memory size 4F Memory size display started This will be updated during memory test Going for sequential and random memory test 50 Memory testing initialization below 1M complete Goin...

Page 104: ...fter setting timer and printer base address Going to set the RS 232 base address 9B Returned after RS 232 base address Going to do any initialization before Coprocessor test 9C Required initialization before Coprocessor is over Going to initialize the Coprocessor next 9D Coprocessor initialized Going to do any initialization after Coprocessor test 9E Initialization after Coprocessor test is comple...

Page 105: ...nd shut down the system if they fail Before shutting down the system the terminal error handler issues a beep code signifying the test point error writes the error to I O port 80h attempts to initialize the video and writes the error in the upper left corner of the screen using both monochrome and color adapters If POST completes normally the BIOS issues one short beep before passing control to th...

Page 106: ...which the control is passed to the different bus routines The high byte of the checkpoint is the indication of which routine is being executed in the different buses Table 73 describes the upper nibble of the high byte and indicates the function that is being executed Table 73 Upper Nibble High Byte Functions Value Description 0 func 0 disable all devices on the bus concerned 1 func 1 static devic...

Page 107: ...voltage for the device 9 2 S875WP1 E Power Budget The following table shows the power consumed on each supply line for a Intel Server Board S875WP1 E that is configured with one Intel Pentium 4 processor pulling max current all PCI slots full and pulling max amount of current memory completely full AGP card installed 4 SATA drives on Promise PDC20319 controller actively running 2 SATA drives hooke...

Page 108: ...tel host system For information on compatible host system s contact your local Intel representative 80 FCC Class A Verification Radiated Conducted Emissions USA 81 ICES 003 Class A Radiated Conducted Emissions Canada 82 CISPR 22 3rd Edition Class A Radiated Conducted Emissions International 83 EN55022 Class A Radiated Conducted Emissions European Union 84 EN55024 Immunity European Union 85 CE EMC ...

Page 109: ...EMC Warning RRL MIC Mark 9 4 Electromagnetic Compatibility Notices 9 4 1 FCC USA This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 this device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation For questions related to the EMC performance of this...

Page 110: ... is responsible for ensuring compliance of the modified product Only peripherals computer input output devices terminals printers etc that comply with FCC Class A or B limits may be attached to this computer product Operation with noncompliant peripherals is likely to result in interference to radio and TV reception All cables used to connect to peripherals must be shielded and grounded Operation ...

Page 111: ...er When the battery starts to weaken it loses voltage and the server settings stored in CMOS RAM in the RTC for example the date and time may be wrong Contact your customer service representative or dealer for a list of approved devices WARNING Danger of explosion if battery is incorrectly replaced Replace only with the same or equivalent type recommended by the equipment manufacturer Discard used...

Page 112: ...eiden mukaisesti 9 6 Calculated Mean Time Between Failures MTBF The MTBF Mean Time Between Failures for the Intel Server Board S875WP1 E as configured from the factory is shown in the table below Product Code Calculated MTBF Operating Temperature S875WP1 216 388 hours 35 degrees C S875WP1LX 203 312 hours 35 degrees C 9 7 Mechanical Specifications The following figure shows the Intel Server Board S...

Page 113: ...S875WP1 E TPS General Specifications Revision 4 0 101 Figure 10 S875WP1 E Server Board Mechanical Drawing ...

Page 114: ... the Intel Server Board S875WP1 E general purpose chassis I O shield mechanical drawing If the Intel Server Board S875WP1 E is used in a 1U chassis the user will need to obtain the I O shield directly from the chassis vendor Figure 11 Intel Server Board S875WP1 E I O Shield Drawing ...

Page 115: ... compatible region of battery backed 128 bytes of memory which normally resides on the server board DCD Data Carrier Detect DMA Direct Memory Access DMTF Distributed Management Task Force ECC Error Correcting Code EMC Electromagnetic Compatibility EPS External Product Specification ESCD Extended System Configuration Data FDC Floppy Disk Controller FIFO First In First Out FRU Field replaceable unit...

Page 116: ...lse Width Modulator RAIDIOS RAID I O Steering RAM Random Access Memory RI Ring Indicate RISC Reduced instruction set computing RMCP Remote Management Control Protocol ROM Read Only Memory RTC Real Time Clock SBE Single Bit Error SCI System Configuration Interrupt SDR Sensor Data Record SDRAM Synchronous Dynamic RAM SEL System event log SERIRQ Serialized Interrupt Requests SERR System Error SM Serv...

Page 117: ...75WP1 E TPS Glossary Revision 4 0 III Term Definition USB Universal Serial Bus VGA Video Graphic Adapter VID Voltage Identification VRM Voltage Regulator Module Word 16 bit quantity ZCR Zero Channel RAID ...

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