Functional Architecture
S875WP1-E TPS
Revision 4.0
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3.7 Clock Generation and Distribution
All buses on the S875WP1-E baseboard operate using synchronous clocks.
Clock
synthesizer/driver circuitry on the baseboard generates clock frequencies and voltage levels as
required, including the following:
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100/133-MHz at 2.5 V & 3.3 V logic levels: For the mPGA478 socket, the MCH, and the
ITP port.
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66 MHz at 3.3 V logic levels: For the MCH and the AGP clocks.
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33.3 MHz at 3.3 V logic levels: For the PCI slots and devices.
•
14.318 MHz at 3.3V logic levels: ICH5-R and Super I/O clocks.
The synchronous clock sources on the S875WP1-E baseboard are:
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100/133-MHz host clock generator for processor, MCH, Memory DIMMs, and the ITP.
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66-MHz clock for MCH and the AGP clocks.
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48-MHz clock for USB.
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33.3-MHz PCI reference clock.
•
14.318 MHz ICH5-R and Super I/O clocks.
The S875WP1-E baseboard also provides asynchronous clock generators:
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25-MHz clocks for the embedded network interface controllers.
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29.498928-MHz clock for the embedded video controller.
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20-MHz clock for the Promise PDC20319 controller.
•
32-KHz clock for the RTC.
3.8 PCI I/O Subsystem
The primary I/O bus for the Intel Server Board S875WP1-E is PCI, with one independent PCI
bus. The PCI bus complies with the
PCI Local Bus Specification, Rev 2.2
. The PCI bus is
directed through the Intel 82801ER I/O Controller Hub (ICH5-R). The table below lists the
characteristics of the PCI bus.
Table 9. PCI Bus Characteristics
Voltage
Width
Speed
Type
Comments
5 V
32-bits
33 MHz
Independent Bus
Supports full-length cards