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Intel S5000VCL - Server Board Motherboard, Technical Product Specification

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Intel

®

 Server Board S5000VCL TPS 

Functional Architecture  

Revision 2.3 

 

 

Intel order number: D64569-007

 

7 

ATI*

ES1000

Video

1333 MT/s

GBE

Serial Port B (Internal)

Serial Port  A (Back Panel)

SATA0
SATA1

PCI-X* 64-bit/133 MHz
PCI-Express x4 (ESB2, Port 1)
PCI-Express x4 (ESB2, Port 2)

Super Slot

PATA

SATA2 / SAS0
SATA3 / SAS1
SATA4 / SAS2
SATA5 / SAS3

LSI* 1064E

PCI-X x4

 

Figure 4. Functional Block Diagram 

Summary of Contents for S5000VCL - Server Board Motherboard

Page 1: ...Intel Server Board S5000VCL Technical Product Specification Intel order number D64569 007 Revision 2 3 May 2007 Enterprise Platforms and Services Division Marketing ...

Page 2: ...must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Server Board S5000VCL may contain design defects or errors known as errata which may cause the product to deviate from publ...

Page 3: ... 3 2 2 Serial ATA Support 13 3 2 3 Parallel ATA PATA Support 14 3 2 4 USB 2 0 Support 14 3 3 Video Support 14 3 4 Network Interface Controller NIC 15 3 4 1 Intel I O Acceleration Technolgy 16 3 5 Super I O 16 4 Platform Management 19 5 Connector Header Locations and Pin outs 20 5 1 Board Connectors 20 5 2 Power Connectors 21 5 3 Riser Card Slots 22 5 4 SSI Control Panel Connector 22 5 5 I O Connec...

Page 4: ...tion 39 8 2 8 Dynamic Loading 40 8 2 9 Capacitive Loading 40 8 2 10 Closed Loop Stability 40 8 2 11 Common Mode Noise 40 8 2 12 Ripple Noise 41 8 2 13 Soft Starting 41 8 2 14 Timing Requirements 41 8 2 15 Residual Voltage Immunity in Standby Mode 43 9 Regulatory and Certification Information 44 9 1 Product Regulatory Compliance 44 9 1 1 Product Safety Compliance 44 9 1 2 Product EMC Compliance Cla...

Page 5: ...able of Contents Revision 2 3 Intel order number D64569 007 v Appendix C POST Error Messages and Handling 53 Appendix D POST Code Diagnostic LED Decoder 56 Appendix E Supported Intel Server Chassis 60 Glossary 62 Reference Documents 65 ...

Page 6: ... Processor Mounting 10 Figure 6 Memory Layout 10 Figure 7 SMBUS Block Diagram 19 Figure 8 Recovery Jumper Blocks J3A1 J1C2 J1C4 29 Figure 9 System Status Fault LED Location 32 Figure 10 DIMM LED Locations 34 Figure 11 POST Code Diagnostic LED Location 35 Figure 12 Output Voltage Timing 42 Figure 13 Turn On Off Timing Power Supply Signals 43 Figure 14 Diagnostic LED Placement Diagram 56 Figure 15 I...

Page 7: ... JA6A1 JA5A1 23 Table 17 44 pin IDE Connector Pin out J2K5 24 Table 18 SATA Connector Pin out J1J2 J1J1 25 Table 19 SATA SAS Connector Pin out J1G2 J1G1 J1F1 J1E4 25 Table 20 9 pin Serial Header Pin out J8A1 J1A1 26 Table 21 Stacked PS 2 Keyboard and Mouse Port Pin out J9A2 26 Table 22 External USB Connector Pin out J9A2 27 Table 23 Internal USB Connector Pin out J3K1 27 Table 24 CPU Fan Connector...

Page 8: ... Intel order number D64569 007 viii Table 39 Turn On Off Timing 42 Table 40 POST Error Messages and Handling 53 Table 41 POST Error Beep Codes 55 Table 42 BMC Beep Codes 55 Table 43 Example POST Progress Code LED 56 Table 44 Diagnostic LED POST Code Decoder 57 ...

Page 9: ...Intel Server Board S5000VCL TPS List of Tables Revision 2 3 Intel order number D64569 007 ix This page intentionally left blank ...

Page 10: ...noted otherwise 1 1 Server Board Use Disclaimer Intel Corporation server boards support add in peripherals and contain high density VLSI and power delivery components that need adequate airflow to cool Intel ensures through its own chassis development and testing that when Intel server building blocks are used together the fully integrated system will meet the intended thermal requirements of thes...

Page 11: ...nnectors for 10 100 1000 Mb connections Two USB 2 0 ports Video connector Com 1 or Serial A DB9 Internal connectors headers One USB port header capable of providing two USB 2 0 ports One DH10 Serial B header Six SATA ports or four SAS ports via the Intel 6321ESB I O Controller Hub These ports support 3Gb s and integrated SW RAID 0 or 1 One 40 pin power I O ATA 100 connector for optical drive suppo...

Page 12: ...System Fault Status LED P SATA 0 C Speaker Q SATA 1 D Super Slot Slot 6 R SSI 24 pin Control Panel Header E External IO Connectors S CPU 1 Fan Header F Main Power Connector T SATA 2 SAS 0 G Power Supply Auxiliary Connector U SATA 3 SAS 1 H CPU Power Connector V SATA 4 SAS 2 I FBDIMM Slots W SATA 5 SAS 3 J CPU Socket 1 X Battery K CPU Socket 2 Y SATA SGPIO L CPU 2 Fan Header Z Serial B Port Header ...

Page 13: ...ed Diagnostics LED Locations AF002053 B D F E C H G A Description Description A Post Code Diagonstic LEDs E CPU 2 Fan Fault LED B System Fault Status LED F CPU 1 Fan Fault LED C CPU 1 Fault LED G System Fan Fault LED D DIMM Fault LEDs H 5 VSB LED E CPU 2 Fault LED Figure 2 Intel Light Guided Diagnostics LED Locations ...

Page 14: ...000VCL TPS Product Overview Revision 2 3 Intel order number D64569 007 5 2 2 2 External I O Connector Locations AF001640 NIC1 10 100 1000 Mb NIC2 10 100 1000 Mb Serial A A C D E F G B Network USB 0 1 Figure 3 ATX I O Layout ...

Page 15: ...5300 series with system bus speeds of 1067 MHz and 1333 MHz The chipset has two main components the Intel 5000V Memory Controller Hub MCH for the host bridge and the Intel 6321ESB I O Controller Hub for the I O subsystem This chapter provides a high level description of the functionality associated with each chipset component and the architectural blocks that make up this server board For in depth...

Page 16: ...64569 007 7 ATI ES1000 Video 1333 MT s GBE Serial Port B Internal Serial Port A Back Panel SATA0 SATA1 PCI X 64 bit 133 MHz PCI Express x4 ESB2 Port 1 PCI Express x4 ESB2 Port 2 Super Slot PAT A SATA2 SAS0 SATA3 SAS1 SATA4 SAS2 SATA5 SAS3 LSI 1064E PCI X x4 Figure 4 Functional Block Diagram ...

Page 17: ...Hz data bus can transfer data at up to 10 66 GB s The MCH supports a 36 bit wide address bus capable of addressing up to 64 GB of memory The MCH is the priority agent for both front side bus interfaces and is optimized for one processor on each bus 3 1 2 Processor Support The server board supports one or two Dual Core Intel Xeon processors 5100 series or low voltage Quad Core Intel Xeon processor ...

Page 18: ...entical revision core voltage and bus core speed When only one processor is installed it must be in the socket labeled CPU1 The other socket must be empty The board provides up to 90A max 70A TDC per processor Processors with higher current requirements are not supported 3 1 2 2 Common Enabling Kit CEK Design Support The server board complies with Intel s common enabling kit CEK processor mounting...

Page 19: ...ers two fully buffered DIMM FBDIMM memory channels FBDIMM memory utilizes a narrow high speed frame oriented interface referred to as a channel The two channels are routed to six DIMM slots and support registered DDR2 667 FBDIMM memory stacked or unstacked Peak FBDIMM memory data bandwidth in dual channel mode is 8 0GB s 2x4 0 GB s with DDR2 667 PC2 5300 3 0 ns at CL5 DIMM B3 DIMM B2 DIMM B1 DIMM ...

Page 20: ...ry Up to six DDR2 667 fully buffered DIMMs FBD memory can be installed Table 3 Maximum Six DIMM System Memory Configuration x4 Single Rank DRAM Technology x4 Single Rank Maximum Capacity Non Mirrored Mode 256 Mb 1 5 GB 512 Mb 3 GB 1024 Mb 6 GB 2048 Mb 12 GB Table 4 Maximum Six DIMM System Memory Configuration x8 Dual Rank DRAM Technology x8 Dual Rank Maximum Capacity Non Mirrored Mode 256 Mb 1 5 G...

Page 21: ...vice that provides four distinct functions an IO Controller a PCI X Bridge a GB Ethernet Controller and a baseboard management controller BMC Each function within the controller hub has its own set of configuration registers Once configured each appears to the system as a distinct hardware controller The controller hub provides the gateway to all PC compatible I O devices and features The server b...

Page 22: ... PCI add in cards on the full height riser card 3 2 1 2 PE2 One x4 PCI Express Bus Segment One x4 PCI Express bus segment is directed through the 6321ESB This PCI Express segment PE2 supports one x8 PCI Express segment to the proprietary I O module mezzanine connector 3 2 1 3 PCI Riser Slot The primary I O buses for this server board supports one Super Slot connector which supports one PCI riser a...

Page 23: ...hat provides I O signals The ATA channel can be configured and enabled or disabled through the BIOS Setup Utility 3 2 4 USB 2 0 Support The USB controller functionality integrated into the 6321ESB provides the interface for up to four USB 2 0 ports Two external connectors are located on the back edge of the server board and one internal 2x5 header supports two optional USB 2 0 ports 3 3 Video Supp...

Page 24: ...emory interface the VGA graphics controller the drawing co processor the display controller the video scalar and the hardware cursor Requests are serviced in a manner that ensures display integrity and maximum CPU co processor drawing performance The server board supports a 16 MB 4 Meg x 16 bit x four banks DDR SDRAM device for video memory 3 4 Network Interface Controller NIC Network interface su...

Page 25: ...n responsiveness across diverse operating systems and virtualized environments Intel I OAT improves network application responsiveness by unleashing the power of Intel Xeon processors through efficient network data movement and reduced system overhead Intel multi port network adapters with Intel I OAT provide high performance I O for server consolidation and virtualization via stateless network ac...

Page 26: ...e 8 Clear To Send CTS 8 Table 9 Internal Serial B Port Header Pin out Pin Signal Name Serial Port A Header Pin out 1 DCD 2 DSR 3 RX 4 RTS 5 TX 6 CTS 7 DTR 8 RI 9 GND Note The RJ45 to DB9 adapter should match the configuration of the serial device used One of two pin out configurations is used depending on whether the serial device requires a DSR or DCD signal The final adapter configuration should...

Page 27: ...an support a mouse or keyboard Neither port supports hot plugging 3 5 1 4 Wake up Control The super I O contains functionality allows events to power on and power off the system 3 5 1 5 System Health Support The super I O provides an interface via GPIOs for BIOS and system management firmware to activate the diagnostic LEDs the FRU fault indicator LEDs for processors FBDIMMS fans and the system st...

Page 28: ...oard management controller BMC features of the Intel 6321ESB I O Controller Hub The onboard platform management subsystem consists of communication buses sensors system BIOS and system management firmware See Appendix B for onboard sensor data For additional platform management information see the Intel 5000 Series Chipsets Server Board Family Datasheet LM4 Figure 7 SMBUS Block Diagram ...

Page 29: ...A3 DIMM Sockets 240 Super Slot 1 J4B2 Card Edge 98 IDE 1 J2K5 Shrouded Header 40 CPU Blowers 1 and 2 2 J2K3 J2K4 Header 4 System Fan 2 J1K1 Header 3 Battery 1 XBT3E1 Battery Holder 3 Keyboard Mouse 1 J9A2 PS2 stacked 12 Rear USB 2 J9A2 External 4 Serial Port A 1 J8A1 External 9 Serial Port B 1 J1A1 Header 9 Video connector 1 J7A1 External D Sub 15 LAN connector 10 100 1000 2 JA6A1 JA5A1 External L...

Page 30: ...e power supply Table 11 Power Connector Pin out J3K3 Pin Signal Color Pin Signal Color 1 3 3Vdc Orange 13 3 3Vdc Orange 2 3 3Vdc Orange 14 12Vdc Blue 3 GND Black 15 GND Black 4 5Vdc Red 16 PS_On Green 5 GND Black 17 GND Black 6 5Vdc Red 18 GND Black 7 GND Black 19 GND Black 8 PWR_OK Gray 20 RSVD_ 5V White 9 5VSB Purple 21 5Vdc Red 10 12Vdc Yellow 22 5Vdc Red 11 12Vdc Yellow 23 5Vdc Red 12 3 3Vdc O...

Page 31: ... 24 pin SSI control panel connector J2K2 for use with non Intel chassis The following table provides the pin out for this connector Table 14 Front Panel SSI Standard 24 pin Connector Pin out J2K2 Pin Signal Name Control Panel Pin out Pin Signal Name 1 P3V3_STBY 2 P3V3_STBY 3 Key 4 P5V_STBY 5 FP_PWR_LED_L 6 FP_ID_LED_L 7 P3V3 8 FP_STATUS_LED1_R 9 HDD_LED_ACT_R 10 FP_STATUS_LED2_R 11 FP_PWR_BTN_L 12...

Page 32: ...d 9 TP_VID_COnN_B9 No Connection 10 GND Ground 11 TP_VID_COnN_B11 No connection 12 V_IO_DDCDAT DDCDAT 13 V_IO_HSYNC_COnN HSYNC horizontal sync 14 V_IO_VSYNC_COnN VSYNC vertical sync 15 V_IO_DDCCLK DDCCLK 5 5 2 NIC Connectors The server board provides two RJ45 NIC connectors oriented side by side on the back edge of the board JA6A1 JA5A1 The pin out for each connector is identical Table 16 RJ 45 10...

Page 33: ... pin IDE Connector Pin out J2K5 Pin Signal Name Pin Signal Name 1 ESB_PLT_RST_IDE_N 2 GND 3 RIDE_DD_7 4 RIDE_DD_8 5 RIDE_DD_6 6 RIDE_DD_9 7 RIDE_DD_5 8 RIDE_DD_10 9 RIDE_DD_4 10 RIDE_DD_11 11 RIDE_DD_3 12 RIDE_DD_12 13 RIDE_DD_2 14 RIDE_DD_13 15 RIDE_DD_1 16 RIDE_DD_14 17 RIDE_DD_0 18 RIDE_DD_15 19 GND 20 KEY 21 RIDE_DDREQ 22 GND 23 RIDE_DIOW_N 24 GND 25 RIDE_DIOR_N 26 GND 27 RIDE_PIORDY 28 GND 29...

Page 34: ...ption 1 GND GND1 2 SATA _TX_P_C Positive side of transmit differential pair 3 SATA _TX_N_C Negative side of transmit differential pair 4 GND GND2 5 SATA _RX_N_C Negative side of Receive differential pair 6 SATA _RX_P_C Positive side of Receive differential pair 7 GND GND3 Table 19 SATA SAS Connector Pin out J1G2 J1G1 J1F1 J1E4 Pin Signal Name Description 1 GND GND1 2 SATA _TX_P_C Positive side of ...

Page 35: ... SPA_RTS RTS request to send 7 SPA_SOUT SOUT serial out 8 SPA_DTR DTR Data terminal ready 9 GND Ground 5 5 6 Keyboard and Mouse Connector Two stacked PS 2 ports J9A2 are support both a keyboard and a mouse Either PS 2 port can support a mouse or a keyboard The following table details the pin out of the PS 2 connector Table 21 Stacked PS 2 Keyboard and Mouse Port Pin out J9A2 Pin Signal Name Descri...

Page 36: ...fferential data line paired with DATAL1 4 GND Ground 5 USB_OC0_LAN USB_Power 6 USB_P0N_LAN DATAH0 Differential data line paired with DATAL0 7 USB_P0P_LAN DATAH0 Differential data line paired with DATAL0 8 GND Ground One 2x5 connector on the server board J3K1 provides an option to support an additional USB 2 0 port Table 23 Internal USB Connector Pin out J3K1 Pin Signal Name Description 1 P5V USB P...

Page 37: ... 12V Power Power supply 12V 3 Fan Tach Out FAN_TACH signal is connected to the BMC to monitor the fan speed 4 Fan PWM In FAN_PWM signal to control fan speed Table 25 PCI Fan Connector Pin out J1K1 Pin Signal Name Type Description 1 Ground GND GROUND is the power supply ground 2 12V Power Power supply 12V 3 Fan Tach Out FAN_TACH signal is connected to the BMC to monitor the fan speed Note Intel Cor...

Page 38: ...bled 1 2 These pins should have a jumper in place for normal system operation Default J1C4 Password Clear 2 3 If these pins are jumpered administrator and user passwords will be cleared on the next reset These pins should not be jumpered for normal operation 1 2 These pins should have a jumper in place for normal system operation Default J1C2 CMOS Clear 2 3 If these pins are jumpered the CMOS sett...

Page 39: ... the firmware to load safely onto the flash device In the unlikely event that the BMC firmware update process fails due to the BMC not being in the proper update state the server board provides a BMC Force Update jumper which will force the BMC into the proper update state The following procedure should be following in the event the standard BMC firmware update process fails 1 Power down and remov...

Page 40: ...ntified by This jumper should only be moved to force the BIOS to boot to the secondary bank which may hold a different version of BIOS The rolling BIOS feature of the server board will automatically alternate the Boot BIOS to the secondary bank if the BIOS image in the primary bank is corrupted and cannot boot Table 27 BIOS Select Jumper J3A2 Pins What happens at system reset 1 2 Force BIOS to ban...

Page 41: ...he Intel 5000 Series Chipsets Server Board Family Datasheet 7 1 5 Volt Standby System Status Fault LED Several system management features of this server board require that 5 volt standby voltage be supplied from the power supply The BMC within the 6321ESB and onboard NICs require this voltage be present when the system is off The 5 volt Standby System Status LED is illuminated when AC power is app...

Page 42: ...o a spare DIMM memory sparing This indicates that the user no longer has spared DIMMs indicating a redundancy lost condition Corresponding DIMM LED should light up In mirrored configuration when memory mirroring takes place and system loses memory redundancy This is not covered by the bullet above Redundancy loss such as power supply or fan This does not apply to non redundant sub systems PCI e li...

Page 43: ... provides a memory fault LED for each DIMM slot The DIMM fault LED is illuminated when the system BIOS disables the specified DIMM after it reaches a specified number of given failures or if specific critical DIMM failures are detected See the Intel 5000 Series Chipsets Server Board Family Datasheet AF001525 A Figure 10 DIMM LED Locations ...

Page 44: ...ode number As each configuration routine is started BIOS will display the given POST code to the POST Code Diagnostic LEDs found on the back edge of the server board To assist in troubleshooting a system hang during the POST process the Diagnostic LEDs can be used to identify the last POST process to be executed See Appendix C for a complete description of how these LEDs are read and for a list of...

Page 45: ...ges Shock Unpackaged Trapezoidal 50 g 170 inches sec Shock Packaged 40 lbs to 80 lbs 24 inches Vibration Unpackaged 5 Hz to 500 Hz 3 13 g RMS random Note 1 The chassis design must provide proper airflow to avoid exceeding the Dual Core Intel Xeon processor 5100 series or Quad Core Intel Xeon processor 5300 series maximum case temperature Disclaimer Note Intel Corporation server boards support add ...

Page 46: ...and Quad Core Intel Xeon processor 5300 series TDP Guidelines TDP Power Max TCASE Icc MAX 108 W 70º C 90 A Note These values are for reference only The Dual Core Intel Xeon processor 5100 series and Quad Core Intel Xeon processor 5300 series Datasheet contains the actual specifications for the processor If the values found in the Dual Core Intel Xeon processor 5100 series Datasheet are different t...

Page 47: ...eak power and current loading shall be supported for a minimum of 12 seconds 8 2 3 Turn On No Load Operation At power on the system shall present a no load condition to the power supply In this no load state the voltage regulation limits for the 3 3V and 5V are relaxed to 10 and the 12V rails relaxed to 10 8 When operating loads are applied the voltages must regulated to there normal limits Table ...

Page 48: ...stem for the 3 3 V output The 5 V 12 V1 12 V2 12 V3 12 V and 5 VSB outputs only use remote sense referenced to the ReturnS signal The remote sense input impedance to the power supply must be greater than 200 on 3 3 VS and 5 VS this is the value of the resistor connecting the remote sense to the output voltage internal to the power supply Remote sense must be able to regulate out a minimum of a 200...

Page 49: ...may happen simultaneously 2 The 12 V should be tested with 2200 F evenly split between the four 12 V rails 8 2 9 Capacitive Loading The power supply shall be stable and meet all requirements with the following capacitive loading ranges Table 36 Capacitive Loading Conditions Output Minimum Maximum Units 3 3 V 250 6 800 F 5 V 400 4 700 F 12 V 500 each 11 000 F 12 V 1 350 F 5 VSB 20 350 F 8 2 10 Clos...

Page 50: ...cified AC line or load conditions There is no requirement for rise time on the 5 V standby but the turn on off shall be monotonic 8 2 14 Timing Requirements These are the timing requirements for the power supply operation The output voltages must rise from 10 to within regulation limits Tvout_rise within 5 to 70 ms except for 5VSB it is allowed to rise from 1 0 to 25 ms All outputs must rise monot...

Page 51: ...wok_holdup Delay from loss of AC to de assertion of PWOK Measured at 75 of maximum load 20 msec Tpson_on_delay Delay from PSOn active to output voltages within regulation limits 5 400 msec T pson_pwok Delay from PSOn deactive to PWOK being de asserted 50 msec Tpwok_on Delay from output voltages within regulation limits to PWOK asserted at turn on 100 500 msec T pwok_off Delay from PWOK de asserted...

Page 52: ...gnals 8 2 15 Residual Voltage Immunity in Standby Mode The power supply shall be immune to any residual voltage placed on its outputs typically a leakage voltage through the system from standby output up to 500 mV There shall be no additional heat generated nor stress of any internal components with this voltage applied to any individual output and all outputs simultaneously It also should not tri...

Page 53: ...d The final configuration of your end system product may require additional EMC compliance testing For more information please contact your local Intel Representative This is an FCC Class A device Integration of it into a Class B chassis does not result in a Class B device 9 1 Product Regulatory Compliance Intended Application This product was evaluated as Information Technology Equipment ITE whic...

Page 54: ...16 91 Emissions Listed on one System License Russia GOST R 50628 95 Immunity Listed on one System License Russia Belarus License Listed on one System License Belarus RRL MIC Notice No 1997 41 EMC 1997 42 EMI Korea 9 1 3 Certifications Registrations Declarations UL Certification or NRTL US Canada CE Declaration of Conformity CENELEC Europe FCC ICES 003 Class A Attestation USA Canada C Tick Declarat...

Page 55: ...Marking UL Mark USA Canada CE Mark Europe EMC Marking Class A Canada CANADA ICES 003 CLASS A CANADA NMB 003 CLASSE A BSMI Marking Class A Taiwan C tick Marking Australia New Zealand RRL MIC Mark Korea Country of Origin Exporting Requirements MADE IN xxxxx Provided by label not silk screen Model Designation Regulatory Identification Examples Intel Server Board S5000VCL for boxed type boards or Boar...

Page 56: ...ce with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of these mea...

Page 57: ...gital Apparatus ICES 003 of the Canadian Department of Communications 9 3 3 Europe CE Declaration of Conformity This product has been tested in accordance too and complies with the Low Voltage Directive 73 23 EEC and EMC Directive 89 336 EEC The product has been marked with the CE Mark to illustrate its compliance 9 3 4 VCCI Japan English translation of the notice above This is a Class B product b...

Page 58: ...oration Refer to country of origin marked on product 9 4 Restriction of Hazardous Substances RoHS Compliance Intel has a system in place to restrict the use of banned substances in accordance with the European Directive 2002 95 EC Compliance is based on declaration that materials banned in the RoHS Directive are either 1 below all applicable substance threshold limits or 2 an approved pending RoHS...

Page 59: ...dware and OS List Only Dual Core Intel Xeon processors 5100 series or low voltage Quad Core Intel Xeon processor 5300 series with system bus speeds of 1066 or 1333 MHz are supported on this server board Previous generation Intel Xeon processors are not supported For a complete list of supported processors see the following link http support intel com support motherboards server S5000VCL Removing A...

Page 60: ... discrete sensors which have only two states Event Offset Triggers Event Thresholds are supported event generating thresholds for threshold types of sensors u l nr c nc upper nonrecoverable upper critical upper noncritical lower nonrecoverable lower critical lower noncritical uc lc upper critical lower critical Event Triggers are supported event generating offsets for discrete type sensors The off...

Page 61: ...ly or automatically This column indicates the type supported by the sensor The following abbreviations are used in the comment column to describe a sensor A Auto rearm M Manual rearm Default Hysteresis Hysteresis setting applies to all thresholds of the sensor This column provides the count of hysterisis for the sensor which can be 1 or 2 positive or negative hysteresis Criticality Criticality is ...

Page 62: ...the Error Manager screen an error is logged to the SEL and the system cannot boot unless the error is resolved The user needs to replace the faulty part and restart the system Table 40 POST Error Messages and Handling Error Code Error Message Response 004C Keyboard interface error Pause 0012 CMOS date time not set Pause 5220 Configuration cleared by jumper Pause 5221 Passwords cleared by jumper Pa...

Page 63: ... DIMM_D3 failed Self Test BIST Pause 852F DIMM_D4 failed Self Test BIST Pause 8540 Memory Component lost redundancy during the last boot Pause 8580 DIMM_A1 Correctable ECC error encountered Pause 8581 DIMM_A2 Correctable ECC error encountered Pause 8582 DIMM_A3 Correctable ECC error encountered Pause 8583 DIMM_A4 Correctable ECC error encountered Pause 8584 DIMM_B1 Correctable ECC error encountere...

Page 64: ...e conditions Beep codes are sounded each time the problem is discovered such as on each power up attempt but are not sounded continuously Codes that are common across all Intel server boards and systems that use the Intel 5000 Series Chipsets are listed in Table 42 Each digit in the code is represented by a sequence of beeps whose count is equal to the digit Table 42 BMC Beep Codes Code Reason for...

Page 65: ...odes are divided into an upper nibble and a lower nibble Each bit in the upper nibble is represented by a red LED and each bit in the lower nibble is represented by a green LED If both bits are set in the upper and lower nibbles then both the red and green LEDs are lit resulting in an amber color If both bits are clear then the LED is off Example The BIOS sends a value of ACh to the diagnostic LED...

Page 66: ...G A Off Optimizing memory controller settings 0x27h Off G A G Initializing memory such as ECC init 0x28h G Off R Off Testing memory PCI Bus 0x50h Off R Off R Enumerating PCI busses 0x51h Off R Off A Allocating resources to PCI busses 0x52h Off R G R Hot Plug PCI controller initialization 0x53h Off R G A Reserved for PCI bus 0x54h Off A Off R Reserved for PCI bus 0x55h Off A Off A Reserved for PCI ...

Page 67: ... fixed media device Removable Media 0xB8h A Off R R Resetting removable media device 0xB9h A Off R A Disabling removable media device 0xBAh A Off A R Detecting presence of a removable media device IDE CDROM detection etc 0xBCh A G R R Enabling configuring a removable media device Boot Device Selection 0xD0 R R Off R Trying boot device selection 0xD1 R R Off A Trying boot device selection 0xD2 R R ...

Page 68: ...e beep unless silent boot is enabled 0xEFh A A A G Unrecoverable boot failure S3 resume failure Runtime Phase EFI Operating System Boot 0xF4h R A R R Entering Sleep state 0xF5h R A R A Exiting Sleep state 0xF8h A R R R Operating system has requested EFI to close boot services ExitBootServices has been called 0xF9h A R R A Operating system has switched to virtual address mode SetVirtualAddressMap h...

Page 69: ...ntel Server Board S5000VCLSASBB BBS5000VCLSASR SAS is supported in the Intel Server System SR1530HCLS SR1530HCLSR See the Intel Server Systems SR1535CL SR1530HCL SR1530HCLS and SR1535CLR SR1530HCLR SR1530HCLSR Technical Product Specification for more information AF001026 F G H A B D E C I A A Rack handles F 400 watt power supply B Slimline drive bay drive not included G Processor air duct C Power ...

Page 70: ...ndles H 400 W power supply B Air baffle I Front panel board C Power supply fans J Control panel D Processor air duct K Hard drive bays drives not included E Full height PCI riser card L Optical drive bay drive not included F Low profile PCI riser card M Hard drive bay drive not included G Intel Server Board S5000VCL Figure 16 Intel Server System SR1530HCL SR1530HCLR ...

Page 71: ...Challenge Handshake Authentication Protocol CMOS In terms of this specification this describes the PC AT compatible region of battery backed 128 bytes of memory which normally resides on the server board DPC Direct Platform Control EEPROM Electrically Erasable Programmable Read Only Memory EHCI Enhanced Host Controller Interface EMP Emergency Management Port EPS External Product Specification ESB2...

Page 72: ...trical resistance PEF Platform Event Filtering PEP Platform Event Paging PIA Platform Information Area This feature configures the firmware for the platform hardware PLD Programmable Logic Device PMI Platform Management Interrupt POST Power On Self Test PSMI Power Supply Management Interface PWM Pulse Width Modulation RAM Random Access Memory RASUM Reliability Availability Serviceability Usability...

Page 73: ...rm Definition TIM Thermal Interface Material UART Universal Asynchronous Receiver Transmitter UDP User Datagram Protocol UHCI Universal Host Controller Interface UTC Universal time coordinare VID Voltage Identification VRD Voltage Regulator Down Word 16 bit quantity ZIF Zero Insertion Force ...

Page 74: ...Intel Server Board S5000VCL TPS Reference Documents Revision 2 3 Intel order number D64569 007 65 Reference Documents Intel 5000 Series Chipsets Server Board Family Datasheet ...

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