Intel S2600WF Series, Technical Product Specification

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Intel® Server Board S2600WF Product Family Technical Product Specification
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B.2. BIOS POST Progress Codes
Table 55 provides a list of all POST progress codes.
Table 55. POST progress codes
Post Code
(Hex)
Upper Nibble Lower Nibble
Description 8h 4h 2h 1h 8h 4h 2h 1h
SEC Phase
01 0 0 0 0 0 0 0 1 First POST code after CPU reset
02 0 0 0 0 0 0 1 0 Microcode load begin
03 0 0 0 0 0 0 1 1 CRAM initialization begin
04 0 0 0 0 0 1 0 0 PEI Cache When Disabled
05 0 0 0 0 0 1 0 1 SEC Core At Power On Begin.
06 0 0 0 0 0 1 1 0 Early CPU initialization during SEC Phase.
KTI RC (Fully leverage without platform change)
A1 1 0 1 0 0 0 0 1 Collect info such as SBSP, boot mode, reset type, etc.
A3 1 0 1 0 0 0 1 1 Setup minimum path between SBSP and other sockets
A6 1 0 1 0 0 1 1 0 Sync up with PBSPs
A7 1 0 1 0 0 1 1 1 Topology discovery and route calculation
A8 1 0 1 0 1 0 0 0 Program final route
A9 1 0 1 0 1 0 0 1 Program final IO SAD setting
AA 1 0 1 0 1 0 1 0 Protocol layer and other uncore settings
AB 1 0 1 0 1 0 1 1 Transition links to full speed operation
AE 1 0 1 0 1 1 1 0 Coherency settings
AF 1 0 1 0 1 1 1 1 KTI initialization done
PEI Phase
10 0 0 0 1 0 0 0 0 PEI Core
11 0 0 0 1 0 0 0 1 CPU PEIM
15 0 0 0 1 0 1 0 1 Platform Type Init
19 0 0 0 1 1 0 0 1 Platform PEIM Init
31 0 0 1 1 0 0 0 1 Memory Installed
32 0 0 1 1 0 0 1 0 CPU PEIM (CPU Init)
33 0 0 1 1 0 0 1 1 CPU PEIM (Cache Init)
34 0 0 1 1 0 1 0 0 CPU BSP Select
35 0 0 1 1 0 1 0 1 CPU AP Init
36 0 0 1 1 0 1 1 0 CPU SMM Init
4F 0 1 0 0 1 1 1 1 DXE IPL started
DXE Phase
60 0 1 1 0 0 0 0 0 DXE Core started
62 0 1 1 0 0 0 1 0 DXE Setup Init
68 0 1 1 0 1 0 0 0 DXE PCI Host Bridge Init
69 0 1 1 0 1 0 0 1 DXE NB Init
6A 0 1 1 0 1 0 1 0 DXE NB SMM Init
70 0 1 1 1 0 0 0 0 DXE SB Init
71 0 1 1 1 0 0 0 1 DXE SB SMM Init
72 0 1 1 1 0 0 1 0 DXE SB devices Init
78 0 1 1 1 1 0 0 0 DXE ACPI Init
79 0 1 1 1 1 0 0 1 DXE CSM Init