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Low Voltage Intel

Pentium

III

Processor 512K Dual Processor
Platform

Design Guide

March 2002

Order Number: 273674-001

Summary of Contents for Pentium III Processor 512K

Page 1: ...Low Voltage Intel Pentium III Processor 512K Dual Processor Platform Design Guide March 2002 Order Number 273674 001...

Page 2: ...tel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or...

Page 3: ...hoot Overshoot Requirements 18 3 9 Debug Port Routing Guidelines 19 3 9 1 Target System Implementation 19 4 0 Clocking 24 4 1 General Clocking Considerations 24 4 2 Single Ended Host Bus Clocking Rout...

Page 4: ...tions 20 7 TCK Termination DP System 21 8 PRDYx Signal Termination 21 9 RESET Signal Termination 22 10 JTAG Signals TDI TDO for Processor Only 23 11 Host Bus Clock Connections 24 12 Single Ended Clock...

Page 5: ...for T Topology 15 9 Wired OR Values 16 10 System Signal Layout Guidelines 20 11 JTAG Signal Layout Guidelines 20 12 Execution Signals Routing Guidelines 21 13 Debug Port Termination Requirement 22 14...

Page 6: ...6 Design Guide LV Intel Pentium III Processor 512K Dual Processor Platform Revision History Date Revision Description March 2002 001 First release of this document...

Page 7: ...ns are suggestions for platform design These provide one way to meet the design recommendations They are based on the reference platforms designed by Intel They could be used as an example but may not...

Page 8: ...i e 1 25 V VTT AGTL technology This processor contains 512 Kbytes of L2 cache is dual processor capable and has a 133 MHz processor side bus Micro FCBGA Micro Flip Chip Ball Grid Array The package te...

Page 9: ...rtant to consider the minimum and maximum impedance of a trace based on the switching of neighboring traces Using wider spaces between the traces can minimize this trace to trace coupling In addition...

Page 10: ...plit on the ground plane layer Keep vias for decoupling capacitors as close to the capacitor pads as possible 2 2 Micro FCBGA Component Keepout Figure 2 shows the keepout zones and dimensions for the...

Page 11: ...idth 7 19 mm e Ball pitch 1 27 mm N Ball count 479 each K Keep out outline from edge of package 5 mm K1 Keep out outline at corner of package 7 mm K2 Capacitor keep out height 0 7 mm S Package edge to...

Page 12: ...III Processor 512K Dual Processor Platform 12 Design Guide This page intentionally left blank Figure 3 Micro FCBGA Package Top and Bottom Isometric Views TOP VIEW BOTTOM VIEW LABEL DIE PACKAGE KEEPOU...

Page 13: ...Equation Tflight min Thold Tco min Tskew Tflight max Tcycle Tco max Tsu Tskew Tjit Tadj Table 4 System Timing Terms Term Description Tcycle System cycle time Defined as the reciprocal of the frequency...

Page 14: ...ocessing platforms use a system bus T topology Figure 4 shows a high level diagram of this topology The pull up resistors shown inside the processor packages are the processor s on die AGTL terminatio...

Page 15: ...the chipset branch of the T topology reduces the effect of multiple driving agents on these signals Intel recommends that system designers carefully examine the signal integrity of these signals and...

Page 16: ...ecommended for high speed system bus designs Start simulations prior to layout Pre layout simulations provide a detailed picture of the working solution space that meets flight time and signal quality...

Page 17: ...t is important to provide effective signal return path with low inductance The best signal routing is directly adjacent to a solid GND plane with no splits or cuts Eliminate parallel traces between la...

Page 18: ...e off for this smaller cross sectional area is a higher trace resistivity that can reduce the falling edge noise margin because of the I R loss along the trace 3 7 Layout Rules for Non AGTL CMOS Signa...

Page 19: ...in the ITP debug system are high speed signals and must be routed with high speed design considerations in mind The implementation offers flexibility in areas such as JTAG routing i e scan chain addit...

Page 20: ...ystem Signal Layout Guidelines Signal Routing Notes Sample Layout POWERON Route with normal trace 2 to 6 inches to the debug port connector Figure 6a BCLK BCLK N A DBRESET BSEN DBINST Figure 6a Figure...

Page 21: ...stem Table 12 Execution Signals Routing Guidelines Signal Routing Notes Sample Layout PREQx AGTL signal routing guidelines apply Figure 6 a PRDYx Figure 8 RESET The flight time of the RESET signal fro...

Page 22: ...13 Debug Port Termination Requirement Signal Signal Termination Value Rt Termination Value Rs Termination Voltage Rt System Signal POWERON 1 5 K N A VTT BCLK BCLK BSEN 240 N A VCC DBRESET 240 N A VCC...

Page 23: ...ssor VERY SENSITIVE TO NOISE please route accordingly TMS TDO TDI POWERON DBRESET BSEN DBINST PREQx Figure 6 a 1 max from debug port to RT AND 12 max from debug port to processor TRST Figure 6 b 1 max...

Page 24: ...an be routed next to clock traces to reduce crosstalk to other signals Figure 11 shows the host bus clocking connections that must be made in a LV Intel Pentium III processor 512K system Detailed info...

Page 25: ...he topology that should be used for the LV Intel Pentium III processor 512K clock traces Please note that L0 L1 and L2 refer to trace lengths between the illustrated components Table 15 contains the r...

Page 26: ...ed at 1 accuracy Match processor 0 and processor 1 L1 lengths as close as possible maximum delta of 0 20 Note The chipset may use a different clock reference level than the processor This difference s...

Page 27: ...input To provide a steady reference voltage a filter circuit must be implemented and attached to this pin Figure 14 shows the recommended CLKREF filter implementation The CLKREF filter should be plac...

Page 28: ...be connected together Instead the BSEL pins on the clock generator should be pulled up to 3 3 V through a 1 K 5 resistor This strapping forces the clock generator into 133 MHz clocking mode and will o...

Page 29: ...Clock trace lengths may be adjusted to center the recovery of BPM 5 0 and RESET at the Debug Port within the ITP receiver setup and hold window For a single ended clock driver design the topology ill...

Page 30: ...etween the processor and its chipset The terms AGTL and system bus are synonymous VRM 8 5 refers to the voltage regulator for the LV Intel Pentium III processor 512K It is a DC DC converter that suppl...

Page 31: ...nt requirements for both processors from one large voltage regulator However due to the load line characteristics specified for the LV Intel Pentium III Processor 512K Intel recommends that separate p...

Page 32: ...2 Multiple Voltages The VRM 8 5 voltage regulator which provides the VccCORE supply to the processor can supply voltages from 1 05 V to 1 825 V The VRM 8 5 voltage regulator can provide adequate powe...

Page 33: ...es the more accurate power distribution model shown in Figure 18 5 4 1 Supplying Voltage Local point of load regulation is recommended for the LV Intel Pentium III processor 512K to satisfy the higher...

Page 34: ...y quick changes in current demand but are also long lasting average current requirements Maintaining voltage tolerance during these changes in current requires high density bulk capacitors with low Ef...

Page 35: ...n begin analog modeling The following sections contain Intel s design recommendations 5 5 1 Decoupling Guidelines for LV Intel Pentium III Processor 512K Designs 5 5 1 1 Decoupling Guidelines The proc...

Page 36: ...PLL1 and PLL2 This serves as an isolated decoupled power source for the internal PLL 5 5 2 1 Topology The LV Intel Pentium III processor 512K has internal phase lock loop PLL clock generators which a...

Page 37: ...nuation in pass band see DC drop in next set of requirements 34 dB attenuation from 1 MHz to 66 MHz 28 dB attenuation from 66 MHz to core frequency The filter specification is shown in Figure 22 Other...

Page 38: ...on boot failures a platform workaround is required The system must provide a rising edge on the TCK signal during the power on sequence that meets all of the following requirements Edge occurs after...

Page 39: ...e PWRGD inputs together in a Wired AND fashion allows each processor to receive PWRGD at the same time but at the latter of the 2 separate PWRGD assertions When separation of the PWRGD inputs to each...

Page 40: ...details AP 1 0 Connect to chipset and second CPU BERR C14 Connect to chipset and second CPU Pull up to VTT through a 150 resistor at the chipset See Wired OR Signal Considerations on page 15 for deta...

Page 41: ...U and pull up through 150 to VccCMOS May need to connect to chipset or server management logic FLUSH AF5 Connect to second CPU and pull up through 150 to VccCMOS IERR AF4 Pull up through 150 to VccCMO...

Page 42: ...e 22 TAP ITP Signals CPU Pin Pin Connection PRDY AE22 Pull up resistor that matches GTL characteristic impedance to VTT 240 series resistor to ITP PREQ AF19 200 300 pull up to VccCMOS and connect to I...

Page 43: ...de anode Connect to thermal sensor device NCHCTRL AD16 Connect to VTT through a 14 1 resistor RTTCTRL AE16 68 1 pull down to GND SLEWCTRL AF16 110 1 pull down to GND VID 3 0 Each VID line must be pull...

Page 44: ...acitor node Ten 10 F X7R 6 3 V 1206 size ceramic capacitors should be placed around the package periphery near the balls Trace lengths to the vias should be designed to minimize inductance Avoid bendi...

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