Intel
®
NetStructure
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ZT 5515 Compute Processor Board Technical Product Specification
41
Watchdog Timer
Watchdog Timer
8
This chapter explains the operation of the ZT 5515’s watchdog timer. It provides an overview of
watchdog operation and features, as well as sample code to help you learn how the watchdog timer
works with applications.
8.1
Watchdog Timer Overview
The primary function of the watchdog timer is to monitor the ZT 5515’s operation and take
corrective action if the software fails to function as programmed. The major features of the
watchdog timer are:
•
Two-stage operation (meaning that it can be enabled to produce a non-maskable interrupt
[NMI] or a “CPU init” before it generates a reset)
•
Enabled and disabled through software control
•
Armed and strobed through software control
The ZT 5515’s custom watchdog timer circuit is implemented in a programmable logic device. The
watchdog timer contains a “Control and Status Register” (see
Section C.1.2, “Watchdog (79h)” on
page 78
for more information). The register allows applications to determine if a watchdog timeout
caused a particular reset.
The watchdog timer drives the First and Second Stages as follows:
1. The watchdog times out (First Stage) after a selected timeout interval.
2. NMI or INIT (software selectable) is driven high.
3. A hard reset occurs (Second Stage) 250 ms later.
Eight timeout intervals are selectable through bits 0-2 of the register. The intervals range from a
minimum of 250 ms to a maximum of 256 seconds. See
Section C.1.2, “Watchdog (79h)” on
page 78
to see all possible timeout periods. A register bit can be enabled to indicate if the watchdog
timer caused the reset event. The watchdog timer register is cleared on power-up, enabling the
system software to take appropriate action if the watchdog generated the reboot.
Figure 7. Watchdog Timer Architecture
Address/Data
Port 79h
Control
and Status
Register
Slow Clock
Counter
Watchdog Circuit
Reset
NMI
CPU Init
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