Intel® Compute Module MFS5520VI TPS
Functional Architecture
Revision 1.5
13
Intel order number: E64311-007
The compute module Quick Reference Label DIMM slot identifiers provide information
about the channel, and therefore the processor to which they belong. For example,
DIMM_A1 is the first slot on Channel A on processor 1; DIMM_D1 is the first DIMM
socket on Channel D on processor 2.
The memory slots associated with a given processor are unavailable if the given
processor socket is not populated.
A processor may be installed without populating the associated memory slots provided a
second processor is installed with associated memory. In this case, the memory is
shared by the processors. However, the platform suffers performance degradation and
latency due to the remote memory.
Processor sockets are self-contained and autonomous. However, all memory subsystem
support (that is, Memory RAS, Error Management, and so on) in the BIOS setup are
applied commonly across processor sockets.
3.2.4
Memory RAS
3.2.4.1
RAS Features
The Compute Module supports the following memory RAS features:
Channel Independent Mode
Channel Mirroring Mode
The memory RAS offered by the Intel
®
Xeon
®
Processor 5500 series and Intel
®
Xeon
®
Processor 5600 series processors is done at channel level, that is, during mirroring, channel B
mirrors channel A. All DIMM matching requirements are on a slot to slot basis on adjacent
channels. For example, to enable mirroring, corresponding slots on channel A and channel B
must have DIMMs of identical parameters.
If one socket fails the population requirements for RAS, the BIOS sets all six channels to the
Channel Independent mode.
The memory slots of DDR3 channels from the Intel
®
Xeon
®
Processor 5500 series and Intel
®
Xeon
®
Processor 5600 series processors should be populated on a farthest first fashion. This
holds true even in the Channel Independent mode. This means that A2 cannot be
populated/used if A1 is empty.
3.2.4.2
Channel Independent Mode
In the Channel Independent mode, multiple channels can be populated in any order (for
example, channels B and C can be populated while channel A is empty). Therefore, all DIMMs
are enabled and utilized in the Channel Independent mode.
3.2.4.3
Channel Mirroring Mode
The Intel
®
Xeon
®
Processor 5500 series and Intel
®
Xeon
®
Processor 5600 series support
channel mirroring to configure available channels of DDR3 DIMMs in the mirrored configuration.
The mirrored configuration is a redundant image of the memory, and can continue to operate
despite the presence of sporadic uncorrectable errors.
Channel mirroring is a RAS feature in which two identical images of memory data are
maintained, thus providing maximum redundancy. On the Intel
®
Xeon
®
Processor 5500 series
and Intel
®
Xeon
®
Processor 5600 series processors based Intel
®
server boards, mirroring is
