Intel M50CYP1UR Series, Integration And Service Manual

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Intel® Server System M50CYP1UR Family System Integration and Service Guide
105
Post
Code
(Hex)
Upper Nibble Lower Nibble
Description
8h 4h 2h 1h 8h 4h 2h 1h
MRC Progress Codes – At this point the MRC Progress Code sequence is executed.
31 0 0 1 1 0 0 0 1 Memory Installed
32 0 0 1 1 0 0 1 0 CPU PEIM (CPU Init)
33 0 0 1 1 0 0 1 1 CPU PEIM (Cache Init)
34 0 0 1 1 0 1 0 0 CPU BSP Select
35 0 0 1 1 0 1 0 1 CPU AP Init
36 0 0 1 1 0 1 1 0 CPU SMM Init
4F 0 1 0 0 1 1 1 1 DXE IPL started
Memory Feature Progress Codes
C1 1 1 0 0 0 0 0 1 Memory POR check
C2 1 1 0 0 0 0 1 0 Internal Use
C3 1 1 0 0 0 0 1 1 Internal Use
C4 1 1 0 0 0 1 0 0 Internal Use
C5 1 1 0 0 0 1 0 1 Memory Early Init
C6 1 1 0 0 0 1 1 0 Display DIMM info in debug mode
C7 1 1 0 0 0 1 1 1 JEDEC Nvdimm training
C9 1 1 0 0 1 0 0 1 Setup SVL and Scrambling
CA 1 1 0 0 1 0 1 0 Internal Use
CB 1 1 0 0 1 0 1 1 Check RAS support
CC 1 1 0 0 1 1 0 0 Pmem ADR Init
CD 1 1 0 0 1 1 0 1 Internal Use
CE 1 1 0 0 1 1 1 0 Memory Late Init
CF 1 1 0 0 1 1 1 1 Determine MRC boot mode
D0 1 1 0 1 0 0 0 0 MKTME Early Init
D1 1 1 0 1 0 0 0 1 SGX Early Init
D2 1 1 0 1 0 0 1 0 Memory Margin Test
D3 1 1 0 1 0 0 1 1 Internal Use
D5 1 1 0 1 0 1 0 1 Internal Use
D6 1 1 0 1 0 1 1 0 Offset Training Result
DXE Phase
60 0 1 1 0 0 0 0 0 DXE Core started
62 0 1 1 0 0 0 1 0 DXE Setup Init
68 0 1 1 0 1 0 0 0 DXE PCI Host Bridge Init
69 0 1 1 0 1 0 0 1 DXE NB Init
6A 0 1 1 0 1 0 1 0 DXE NB SMM Init
70 0 1 1 1 0 0 0 0 DXE SB Init
71 0 1 1 1 0 0 0 1 DXE SB SMM Init
72 0 1 1 1 0 0 1 0 DXE SB devices Init
78 0 1 1 1 1 0 0 0 DXE ACPI Init
79 0 1 1 1 1 0 0 1 DXE CSM Init
7D 0 1 1 1 1 1 0 1 DXE Removable Media Detect
7E 0 1 1 1 1 1 1 0 DXE Removable Media Detected
90 1 0 0 1 0 0 0 0 DXE BDS started
91 1 0 0 1 0 0 0 1 DXE BDS connect drivers
92 1 0 0 1 0 0 1 0 DXE PCI bus begin