Intel Itanium 9150M, Manual

Page: 283 / 420

3:274 Volume 3: Instruction Reference
xchg
xchg — Exchange
Format: (
qp
) xchg
sz
.
ldhint r
1
= [
r
3
],
r
2
M16
Description:
A value consisting of
sz
bytes is read from memory starting at the address specified by
the value in GR
r
3
. The least significant sz bytes of the value in GR r
2
are written to
memory starting at the address specified by the value in GR r
3
. The value read from
memory is then zero extended and placed in GR r
1
and the NaT bit corresponding to GR
r
1
is cleared. The values of the
sz
completer are given in Table 2-60 .
If the address specified by the value in GR
r
3
is not naturally aligned to the size of the
value being accessed in memory, an Unaligned Data Reference fault is taken
independent of the state of the User Mask alignment checking bit, UM.ac (PSR.ac in the
Processor Status Register).
Both read and write access privileges for the referenced page are required.
The exchange is performed with acquire semantics, i.e., the memory read/write is
made visible prior to all subsequent data memory accesses. See
Section 4.4.7,
“Sequentiality Attribute and Ordering” on page 2:82 for details on memory ordering.
The memory read and write are guaranteed to be atomic.
This instruction is only supported to cacheable pages with write-back write policy.
Accesses to NaTPages cause a Data NaT Page Consumption fault. Accesses to pages
with other memory attributes cause an Unsupported Data Reference fault.
The value of the
ldhint
completer specifies the locality of the memory access. The values
of the
ldhint
completer are given in Table 2-34 on page 3:152 . Locality hints do not
affect program functionality and may be ignored by the implementation. See
Section 4.4.6, “Memory Hierarchy Control and Consistency” on page 1:69 for details.
Table 2-60. Memory Exchange Size
sz Completer Bytes Accessed
1 1 byte
2 2 bytes
4 4 bytes
8 8 bytes