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Intel Desktop Board D810E2CA3 Technical Product Specification 

22  

1.6.1 USB 

 

The ICH2 contains two separate USB controllers supporting four USB ports.  Two of the ports are 
accessible through stacked back panel connectors and the other two are accessible through the 
front panel USB connector at location J8B1.  One USB peripheral can be connected to each port.  
For more than four USB devices, an external hub can be connected to any of the ports.  The board 
fully supports Universal Hub Controller Interface (UHCI) and uses UHCI-compatible software 
drivers. 

✏

 

NOTE 

Computer systems that have an unshielded cable attached to a USB port may not meet 
FCC Class B requirements, even if no device or a low-speed USB device is attached to the cable.  
Use shielded cable that meets the requirements for full-speed devices. 

 

For information about  

Refer to 

The location of the back panel USB connectors  

Figure 8, page 49 

The signal names of the USB connectors 

Table 21, page 50 

The location of the front panel USB connector  

Figure 11, page 63 

The signal names of the front panel USB connector 

Table 41, page 64 

The USB and UHCI specifications  

Section 1.3, page 16 

1.6.2 IDE 

Interfaces 

The ICH2’s IDE controller has two independent bus-mastering IDE interfaces that can be 
independently enabled.  The IDE interfaces support the following modes: 

• 

Programmed I/O (PIO):  processor controls data transfer. 

• 

8237-style DMA:  DMA offloads the processor, supporting transfer rates of up to 16 MB/sec. 

• 

Ultra DMA:  DMA protocol on IDE bus supporting host and target throttling and transfer rates 
of up to 33 MB/sec. 

• 

ATA-66:  DMA protocol on IDE bus supporting host and target throttling and transfer rates of 
up to 66 MB/sec.  ATA-66 protocol is similar to Ultra DMA and is device driver compatible.  
ATA-66 uses faster timings and requires a specialized cable to reduce reflections, noise, and 
inductive coupling. 

• 

ATA-100:  DMA protocol on IDE bus allows host and target throttling.  The ICH2 ATA-100 
logic can achieve read transfer rates up to 100 MB/sec and write transfer rates up to 
88 MB/sec.   

✏

 

NOTE 

ATA-100 and ATA-66 use faster timings and require a specialized cable to reduce reflections, 
noise, and inductive coupling. 

The IDE interfaces also support ATAPI devices (such as CD-ROM drives) and ATA devices using 
the transfer modes listed in Table 66 on page 95. 

The BIOS supports Logical Block Addressing (LBA) and Extended Cylinder Head Sector (ECHS) 
translation modes.  The drive reports the transfer rate and translation mode to the BIOS.  

Summary of Contents for D810E2CA3

Page 1: ...rder Number A43979 001 The Intel Desktop Board D810E2CA3 may contain design defects or errors known as errata that may cause the product to deviate from published specifications Current characterized errata are documented in the Intel Desktop Board D810E2CB Specification Update ...

Page 2: ... and information does not provide any license express or implied by estoppel or otherwise to any such patents trademarks copyrights or other intellectual property rights Intel products are not intended for use in medical life saving or life sustaining applications or for any other application in which the failure of the Intel product could create a situation where personal injury or death may occu...

Page 3: ...Contains Chapter Description 1 A description of the hardware used on this board 2 A map of the resources of the board 3 The features supported by the BIOS Setup program 4 The contents of the BIOS Setup program s menus and submenus 5 A description of the BIOS error messages beep codes and Power On Self Test POST codes Typographical Conventions This section contains information about the conventions...

Page 4: ...tion For example J5J1 is a connector located at 5J It is the first connector in the 5J area GB Gigabyte 1 073 741 824 bytes KB Kilobyte 1024 bytes Kbit Kilobit 1024 bits kbits sec 1000 bits per second MB Megabyte 1 048 576 bytes MB sec Megabytes per second Mbit Megabit 1 048 576 bits Mbit sec Megabits per second xxh An address or data value ending with a lowercase h indicates a hexadecimal value x...

Page 5: ... 4 Keyboard and Mouse Interface 25 1 8 Graphics Subsystem 26 1 8 1 Integrated Graphics Controller 26 1 8 2 Digital Video Output DVO Connector Optional 28 1 9 Audio Subsystem 29 1 9 1 AD1885 Analog Codec 29 1 9 2 Audio Connectors 30 1 10 LAN Subsystem Optional 31 1 10 1 Intel 82562ET Platform LAN Connect Device 31 1 10 2 RJ 45 LAN Connector LEDs 31 1 11 CNR Optional 32 1 12 Hardware Management Subs...

Page 6: ...hermal Considerations 73 2 13 Reliability 74 2 14 Environmental Specifications 75 2 15 Regulatory Compliance 75 2 15 1 Safety Regulations 75 2 15 2 EMC Regulations 76 2 15 3 Product Certification Markings Board Level 76 3 Overview of BIOS Features 3 1 Introduction 77 3 2 BIOS Flash Memory Organization 77 3 3 Resource Configuration 78 3 3 1 PCI Autoconfiguration 78 3 3 2 IDE Support 78 3 4 System M...

Page 7: ...d Beep Codes 5 1 BIOS Error Messages 103 5 2 Port 80h POST Codes 105 5 3 Bus Initialization Checkpoints 109 5 4 Speaker 110 5 5 BIOS Beep Codes 111 Figures 1 D810E2CA3 Board Components 14 2 Board Block Diagram 15 3 Intel 810E2 Chipset Block Diagram 21 4 Block Diagram of Audio Subsystem 29 5 ICH2 and CNR Signal Interface 32 6 Using the Wake on LAN Technology Connector 39 7 Location of Standby Power...

Page 8: ...VGA Connector 51 23 Parallel Port Connector 51 24 Serial Port A Connector 52 25 Audio Line Out Connector 52 26 Audio Line In Connector 52 27 Audio Mic In Connector 52 28 ATAPI CD ROM Connector J2D1 55 29 Front Panel Audio Connector J2E1 55 30 Auxiliary Line In Connector J2E2 55 31 Optional Digital Video Out Connector J2G2 56 32 Processor Fan Connector J2K1 56 33 Chassis Fan Connector J2G1 56 34 Po...

Page 9: ...nu 89 62 PCI Configuration Submenu 90 63 Boot Setting Configuration Submenu 91 64 Peripheral Configuration Submenu 92 65 IDE Device Configuration 94 66 IDE Configuration Submenus 95 67 Diskette Configuration Submenu 96 68 Event Log Configuration Submenu 97 69 Video Configuration Submenu 98 70 Security Menu 99 71 Power Menu 100 72 Boot Menu 101 73 Exit Menu 102 74 BIOS Error Messages 103 75 Uncompr...

Page 10: ...Intel Desktop Board D810E2CA3 Technical Product Specification x ...

Page 11: ...1 3 Design Specifications 16 1 4 Processor 19 1 5 System Memory 20 1 6 Intel 810E2 Chipset 21 1 7 I O Controller 24 1 8 Graphics Subsystem 26 1 9 Audio Subsystem 29 1 10 LAN Subsystem Optional 31 1 11 CNR Optional 32 1 12 Hardware Management Subsystem Optional 33 1 13 Power Management Features 34 ...

Page 12: ...C LPC47M102 low pin count LPC interface I O controller Video Intel 82810E DC 133 Graphics and Memory Controller Hub integrated in the chipset with an optional 4 MB of 133 MHz display cache Audio Intel 82801BA ICH2 digital controller AC link output Analog Devices AD1885 Audio Codec Peripheral Interfaces Four Universal Serial Bus USB ports Two IDE interfaces with Ultra DMA ATA 66 100 support One dis...

Page 13: ...ailable to you Table 2 Manufacturing Options Video Digital video output DVO connector Hardware Monitor Subsystem Wired for Management WfM compliant Voltage sensor to detect out of range values Communication and Networking Riser CNR Connector One CNR connector shared with slot 4 LAN Subsystem Intel 82562ET 10 100 Mbit sec Platform LAN Connect PLC device Wake on LAN Technology Connector Support for ...

Page 14: ... I O controller O Intel 82801BA I O Controller Hub ICH2 D Back panel connectors P Intel 82802AB Firmware Hub FWH E DVO connector optional Q Battery F Processor socket G DIMM sockets R Intel 82810E DC 133 Graphics and Memory Controller Hub GMCH H Power connector S PCI bus add in card connectors I Diskette drive connector T 4 MB display cache optional J Speaker K Secondary IDE connector U Communicat...

Page 15: ...F004A Firmware Hub FWH 100 MHz SDRAM Bus AHA Bus 4 MB Display Cache Optional OM11131 Diskette Drive Connector LPC I O Controller PS 2 Keyboard PS 2 Mouse Parallel Port Serial Port A Serial Port B LPC Bus SMBus PCI Bus PCI Slot 1 PCI Slot 2 PCI Slot 3 PCI Slot 4 DVO Connector Optional Digital Video Output USB Ports 0 and 1 USB Ports 2 and 3 VGA Port Audio Codec Line Out Line In Mic In CD ROM Auxili...

Page 16: ...ard Table 3 Specifications Reference Name Specification Title Version Revision Date and Ownership The information is available from AC 97 Audio Codec 97 Version 2 1 May 1998 Intel Corporation ftp download intel com ial scalableplatforms ac97r22 pdf ACPI Advanced Configuration and Power Interface Specification Version 2 0 July 27 2000 Compaq Computer Corp Intel Corporation Microsoft Corporation and...

Page 17: ...sion 1 7 1997 Institute of Electrical and Electronic Engineers http standards ieee org reading ieee std_public description busarch 1284 1 1997_desc html El Torito Bootable CD ROM Format Specification Version 1 0 January 25 1995 Phoenix Technologies Ltd and IBM Corporation http www ptltd com techs specs html LPC Low Pin Count Interface Specification Version 1 0 September 29 1997 Intel Corporation h...

Page 18: ...stem Management BIOS Version 2 3 1 March 16 1999 American Megatrends Inc Award Software International Inc Compaq Computer Corporation Dell Computer Corporation Hewlett Packard Company Intel Corporation International Business Machines Corporation Phoenix Technologies Limited and SystemSoft Corporation http developer intel com ial wfm design smbios UHCI Universal Host Controller Interface Design Gui...

Page 19: ...he board supports the processors listed in Table 4 Table 4 Supported Processors Processor Speed Processor Speed System Bus Frequency L2 Cache Size 500E 550E 600 650 700 750 800 and 850 MHz 100 MHz 256 KB 533EB 600EB 667 733 800EB 866 and 933 MHz 133 MHz 256 KB Pentium III processor 1 0B GHz 133 MHz 256 KB 400 433 466 500 533A 566A 600 633 667 700 733 and 766 MHz 66 MHz 128 KB Celeron processor in ...

Page 20: ...ipset to accurately configure memory settings for optimum performance If non SPD memory is installed the BIOS will attempt to correctly configure the memory settings but performance and reliability may be impacted The board has two DIMM sockets SDRAM can be installed in one or both sockets Minimum memory size is 64 MB maximum memory size is 512 MB The BIOS automatically detects memory type size an...

Page 21: ...s and the Accelerated Hub Architecture bus The ICH2 is a centralized controller for the board s I O paths The FWH provides the nonvolatile storage of the BIOS The component combination provides the interfaces as shown in Figure 3 810E2 Chipset 82801BA I O Controller Hub ICH2 82810E Graphics Memory Controller Hub GMCH SST 49LF004A Firmware Hub FWH 100 MHz SDRAM Bus AHA Bus ATA 66 100 USB 66 100 133...

Page 22: ...1 6 2 IDE Interfaces The ICH2 s IDE controller has two independent bus mastering IDE interfaces that can be independently enabled The IDE interfaces support the following modes Programmed I O PIO processor controls data transfer 8237 style DMA DMA offloads the processor supporting transfer rates of up to 16 MB sec Ultra DMA DMA protocol on IDE bus supporting host and target throttling and transfer...

Page 23: ...of battery backed CMOS SRAM in two banks that are reserved for BIOS use The time date and CMOS values can be specified in the Setup program The CMOS values can be returned to their defaults by using the Setup program NOTE If the battery and AC power fail custom defaults if previously saved will be loaded into CMOS SRAM at power on A coin cell battery powers the real time clock and CMOS memory When...

Page 24: ...ts Serial port A is located on the back panel Serial port B is accessible using the connector at location J1E2 The serial ports NS16C550 compatible UARTs support data transfers at speeds up to 115 2 kbits sec with BIOS support The serial ports can be assigned as COM1 3F8h COM2 2F8h COM3 3E8h or COM4 2E8h For information about Refer to The location of the serial port A connector Figure 8 page 49 Th...

Page 25: ...ke a self healing fuse reestablishes the connection after an overcurrent condition is removed NOTE The keyboard is supported in the bottom PS 2 connector and the mouse is supported in the top PS 2 connector Power to the computer should be turned off before a keyboard or mouse is connected or disconnected The keyboard controller contains code that provides the traditional keyboard and mouse control...

Page 26: ...leration Motion video acceleration 3 D graphics visual and texturing enhancements Display Integrated 24 bit 230 MHz RAMDAC Display Data Channel Standard Version 3 0 Level 2B protocols compliant see Section 1 3 for specification information Video Hardware motion compensation for software MPEG2 decode Software DVD at 30 fps Integrated graphics memory controller 4 MB of 133 MHz onboard video display ...

Page 27: ... colors 70 D 64 K colors 70 D3 352 x 576 16 M colors 70 D 256 colors 70 D 64 K colors 70 D3 400 x 300 16 M colors 70 D 256 colors 70 D 64 K colors 70 D3 512 x 384 16 M colors 70 D 256 colors 70 D 64 K colors 70 D3 640 x 400 16 M colors 70 D 256 colors 60 70 72 75 85 KDO 64 K colors 60 75 85 KD3O 640 x 480 64 K colors 70 72 KDO 640 x 480 16 M colors 60 70 72 75 85 KDO 256 colors 60 70 72 75 85 KDO ...

Page 28: ...pes of displays unless indicated otherwise NOTE Some of the system memory is reserved for video 1 8 2 Digital Video Output DVO Connector Optional The board routes the Intel 82810E GMCH DVO port to an onboard 40 pin DVO connector The DVO connector can be cabled to a DVI or TV out card to enable digital displays or TV out functionality The Digital Visual Interface DVI specification provides a high s...

Page 29: ...utilities Section 1 2 page 16 Obtaining the AC 97 specification Table 3 page 16 1 9 1 AD1885 Analog Codec The AD1885 is a fully AC 97 compliant codec The codec s features include 90 dB signal to noise ratio sound quality Power management support for APM 1 2 and ACPI 2 0 driver dependent Playback sample rates up to 48 kHz 16 bit stereo full duplex operation Software compatible with Windows 98 SE Wi...

Page 30: ...nnects an internal ATAPI CD ROM drive to the audio mixer For information about Refer to The location of the ATAPI CD ROM connector Figure 9 page 54 The signal names of the ATAPI CD ROM connector Table 28 page 55 1 9 2 2 Front Panel Audio Connector A 2 x 5 pin connector for routing mic in and line out to the front panel For information about Refer to The location of the front panel audio connector ...

Page 31: ...face to the back panel RJ 45 connector with integrated LEDs This physical interface may alternately be provided using the CNR connector The Intel 82562ET provides the following functions Basic 10 100 Ethernet LAN Connectivity Supports RJ 45 connector with status indicator LEDs Full driver compatibility Advanced Power Management support Programmable transit threshold Configuration EEPROM that conta...

Page 32: ...aces supported by the CNR connector include but are not limited to the following AC 97 interface supports audio and or modem functions on the CNR board LAN interfaces an eight pin interface for use with Platform LAN Connection PLC based devices SMBus interface provides Plug and Play functionality for the CNR board USB interface provides a USB interface for the CNR board To learn more about the CNR...

Page 33: ...onal hardware monitor component provides low cost instrumentation capabilities The features of the component include Internal ambient temperature sensing Remote thermal diode sensing for direct monitoring of processor temperature Power supply monitoring 12 V 5 V 3 3 V 2 5 V 3 3 VSB and VCCP to detect levels above or below acceptable values SMBus interface 1 12 2 Fan Control and Monitoring The SMSC...

Page 34: ...tandby mode can be initiated in the following ways Time out period specified in the BIOS Setup program From the operating system such as the Suspend menu item in Windows 98 In standby mode the board can reduce power consumption by spinning down hard drives and reducing power to or turning off VESA DPMS compliant monitors Power management mode can be enabled or disabled in the BIOS Setup program Wh...

Page 35: ...n wake up the computer from this state Power switch Soft off RTC alarm Soft off suspend LAN Soft off suspend PME Soft off suspend USB Suspend PS 2 Suspend Unattended Wake Mode display will be video BIOS string only For information about Refer to Enabling or disabling power management in the BIOS Setup program Section 4 6 page 100 The board s compliance level with APM Table 3 page 16 ...

Page 36: ...s of Pressing the Power Switch If the system is in this state and the power switch is pressed for the system enters this state Off ACPI G2 G5 Soft off Less than four seconds Power on ACPI G0 working state On ACPI G0 working state Less than four seconds Soft off Standby ACPI G1 sleeping state On ACPI G0 working state More than four seconds Fail safe power off ACPI G2 G5 Soft off Sleep ACPI G1 sleep...

Page 37: ...by battery or external source No power to the system so that service can be performed Notes 1 Total system power is dependent on the system configuration including add in boards and peripherals powered by the system chassis power supply 2 Dependent on the standby power consumption of wake up devices used in the system 1 13 1 2 2 Wake Up Devices and Events Table 11 lists the devices or specific eve...

Page 38: ...type of telephony device external or internal and the power management mode being used APM or ACPI NOTE The use of Resume on Ring technology from an ACPI state requires the support of an operating system that provides full ACPI functionality 1 13 2 1 Power Connector When used with an ATX compliant power supply that supports remote power on off the board can turn off the system power through softwa...

Page 39: ...echnology enables remote wakeup of the computer through a network The LAN subsystem whether onboard or as a PCI bus network adapter monitors network traffic at the Media Independent Interface Upon detecting a Magic Packet frame the LAN subsystem asserts a wakeup signal that powers up the computer Depending on the LAN implementation the board supports Wake on LAN technology in the following ways Th...

Page 40: ...mputer will appear to be off the power supply is off the fans are off and the front panel LED is amber if dual color or off if single color When signaled by a wake up device or event the system quickly returns to its last known wake state Table 11 on page 37 lists the devices and events that can wake the computer from the S3 state The board supports the PCI Bus Power Management Interface Specifica...

Page 41: ... summarized as follows Resumes operation from either the APM sleep mode or the ACPI S1 state Requires only one call to access the computer Detects incoming call similarly for external and internal modems Requires modem interrupt be unmasked for correct operation 1 13 2 6 Wake from USB USB bus activity wakes the computer from an ACPI S1 or S3 state NOTE Wake from USB requires the use of a USB perip...

Page 42: ...uct Specification 42 1 13 2 7 Wake from PS 2 Keyboard PS 2 keyboard activity wakes the computer from an ACPI S1 or S3 state 1 13 2 8 PME Wakeup Support When the PME signal on the PCI bus is asserted the computer wakes from an ACPI S1 or S3 state ...

Page 43: ...le 15 lists the DMA channels Table 16 defines the PCI configuration space map and Table 17 describes the interrupts The remaining sections in this chapter are introduced by text found with their respective section headings 2 2 Memory Map Table 13 System Memory Map Address Range decimal Address Range hex Size Description 1024 K 524288 K 100000 1FFFFFFF 511 MB Extended memory 960 K 1024 K F0000 FFFF...

Page 44: ...mpatible 0228 022F Note 1 8 bytes LPT3 0278 027F Note 1 8 bytes LPT2 02E8 02EF Note 1 8 bytes COM4 video 8514A 02F8 02FF Note 1 8 bytes COM2 0376 1 byte Secondary IDE channel command port 0377 bits 6 0 7 bits Secondary IDE channel status port 0 378 037F 8 bytes LPT1 0388 038B 6 bytes AdLib FM synthesizer 03B0 03BB 12 bytes Intel 82810E DC 133 GMCH 03C0 03DF 32 bytes Intel 82810E DC 133 GMCH 03E8 0...

Page 45: ...visible boundary ICH2 USB controller 2 16 contiguous bytes starting on a 16 byte divisible boundary ICH2 SMB 4096 contiguous bytes starting on a 4096 byte divisible boundary Intel 82801BA PCI bridge 64 contiguous bytes starting on a 64 byte divisible boundary Intel 82562ET LAN controller optional Notes 1 Default but can be changed to another address range 2 Dword access only 3 Byte access only NOT...

Page 46: ...00 Intel 82562ET LAN controller optional 01 09 00 PCI bus connector 1 J3D1 01 0A 00 PCI bus connector 2 J3C1 01 0B 00 PCI bus connector 3 J3B1 01 0C 00 PCI bus connector 4 J3A2 2 6 Interrupts Table 17 Interrupts IRQ System Resource NMI I O channel check 0 Reserved interval timer 1 Reserved keyboard buffer full 2 Reserved cascade interrupt from slave PIC 3 COM2 Note user available if COM2 is not pr...

Page 47: ...ammable interrupt request PIRQ input signals All PCI interrupt sources either onboard or from a PCI add in card connect to one of these PIRQ signals Some PCI interrupt sources are electrically tied together on the D810E2CA3 board and therefore share the same interrupt Table 18 shows an example of how the PIRQ signals are routed on the D810E2CA3 board For example using Table 18 as a reference assum...

Page 48: ...ces themselves This section describes the board s connectors The connectors can be divided into the following groups Back panel I O connectors see page 49 PS 2 keyboard and mouse LAN optional USB two VGA Parallel port Serial port A Audio line out line in and mic in Internal I O connectors see page 53 Audio ATAPI CD ROM ATAPI style auxiliary line in front panel audio Digital video interface optiona...

Page 49: ...M11032 B A E J K I H G F D C Item Description Color For more information see A PS 2 mouse Green Table 19 B PS 2 keyboard Purple Table 19 C RJ 45 LAN Black Table 20 D USB port 0 Black Table 21 E USB port 1 Black Table 21 F Parallel port Burgundy Table 23 G VGA port Dark blue Table 22 H Serial port A Teal Table 24 I Audio line in Lime green Table 25 J Audio line out Light blue Table 26 K Mic in Pink...

Page 50: ...nal 1 Data 2 Not connected 3 Ground 4 5 V fused 5 Clock 6 Not connected Table 20 RJ 45 LAN Connector Optional Pin Signal Name 1 TxD 2 TxD 3 RxD 4 Ground 5 Ground 6 RxD 7 Ground 8 Ground Table 21 USB Connectors Pin Signal 1 5 V fused 2 USBP0 USBP1 3 USBP0 USBP1 4 Ground Signal names in brackets are for USB ports 1 ...

Page 51: ...ctor Pin Std Signal ECP Signal EPP Signal I O 1 STROBE STROBE WRITE I O 2 PD0 PD0 PD0 I O 3 PD1 PD1 PD1 I O 4 PD2 PD2 PD2 I O 5 PD3 PD3 PD3 I O 6 PD4 PD4 PD4 I O 7 PD5 PD5 PD5 I O 8 PD6 PD6 PD6 I O 9 PD7 PD7 PD7 I O 10 ACK ACK INTR I 11 BUSY BUSY PERIPHACK WAIT I 12 PERROR PE ACKREVERSE PE I 13 SELECT SELECT SELECT I 14 AUDOFD AUDOFD HOSTACK DATASTB O 15 FAULT FAULT PERIPHREQST FAULT I 16 INIT INI...

Page 52: ...Terminal Ready 5 Ground 6 DSR Data Set Ready 7 RTS Request to Send 8 CTS Clear to Send 9 RI Ring Indicator Table 25 Audio Line Out Connector Pin Signal Tip Audio left out Ring Audio right out Sleeve Ground Table 26 Audio Line In Connector Pin Signal Tip Audio left in Ring Audio right in Sleeve Ground Table 27 Audio Mic In Connector Pin Signal Tip Mono in Ring Mic bias voltage Sleeve Ground ...

Page 53: ...oups Audio video power and hardware control see page 54 ATAPI CD ROM Front panel audio Auxiliary line in ATAPI style Digital video out optional Fans two Power Wake on LAN technology optional Add in boards and peripheral interfaces see page 58 CNR communication and networking riser optional PCI bus four Diskette drive IDE two ...

Page 54: ... 1 1 1 1 1 10 9 2 1 B A Item Description Reference Designator For more information see A ATAPI CD ROM black J2D1 Table 28 B Front panel audio J2E1 Table 29 C Auxiliary line in ATAPI style white J2E2 Table 30 D Digital video out Optional J2G2 Table 31 E Chassis fan Fan 2 J2G1 Table 32 F Processor fan Fan 1 J2K1 Table 33 G Power J8G1 Table 34 H Wake on LAN technology J7A1 Table 35 Figure 9 Audio Vid...

Page 55: ... ground 4 Right audio input from CD ROM Table 29 Front Panel Audio Connector J2E1 Pin Signal Name Pin Signal Name 1 MICIN_FP 2 Ground 3 MIC_BIAS 4 AUD_ANALOG 5 AUD_FPOUT_R 6 AUD_RET_R 7 Reserved 8 Pin removed 9 AUD_FPOUT_L 10 AUD_RET_L Table 30 Auxiliary Line In Connector J2E2 Pin Signal 1 Left auxiliary line in 2 Ground 3 Ground 4 Right auxiliary line in ...

Page 56: ...12 LTVDAT0 13 Ground 14 LTVDAT1 15 Ground 16 LTVDAT2 17 Ground 18 LTVDAT3 19 Ground 20 LTVDAT4 21 Ground 22 LTVDAT5 23 Ground 24 LTVDAT6 25 Ground 26 LTVDAT7 27 Ground 28 LTVDAT8 29 Ground 30 LTVDAT9 31 Ground 32 LTVDAT10 33 Ground 34 LTVDAT11 35 Ground 36 LTVCLKOUT0 37 Ground 38 LTVCLKOUT1 39 Ground 40 LTVBLNK Table 32 Processor Fan Connector J2K1 Pin Signal 1 Ground 2 12 V 3 Ground Table 33 Chas...

Page 57: ...3 3 V 2 3 3 V 12 12 V 3 Ground 13 Ground 4 5 V 14 PS ON power supply remote on off 5 Ground 15 Ground 6 5 V 16 Ground 7 Ground 17 Ground 8 PWRGD Power Good 18 Reserved 9 5 VSB 19 5 V 10 12 V 20 5 V Table 35 Optional Wake on LAN Technology Connector J7A1 Pin Signal 1 5 VSB 2 Ground 3 WOL ...

Page 58: ...ort to access sensor data on the board The specific SMBus signals are as follows The SMBus clock line is connected to pin A40 The SMBus data line is connected to pin A41 OM11034 F H G C B E D 1 2 33 34 1 2 40 39 1 2 40 39 A Item Description Reference Designator For more information see A CNR optional J3A1 Table 36 B PCI bus connector 4 J3A2 Table 37 C PCI bus connector 3 J3B1 Table 37 D PCI bus co...

Page 59: ... LAN_TXD0 B8 LAN_TXD1 A9 Ground B9 LAN_RSTSYNC A10 LAN_CLK B10 Ground A11 LAN_RXD1 B11 LAN_RXD2 A12 Reserved B12 LAN_RXD0 A13 USB B13 Ground A14 Ground B14 Reserved A15 USB B15 5V dual A16 12V B16 USB_OC A17 Ground B17 Ground A18 3 3V dual B18 12V A19 5VD B19 3 3V A20 Ground B20 Ground A21 EEDI B21 EED0 A22 EECS B22 EECK A23 SMB_A1 B23 Ground A24 SMB_A2 B24 SMB_A0 A25 SMB_SDA B25 SMB_SCL A26 AC97_...

Page 60: ...5 B44 C BE1 A14 3 3 V aux B14 Reserved A45 3 3 V B45 AD14 A15 RST B15 Ground A46 AD13 B46 Ground A16 5 V I O B16 CLK A47 AD11 B47 AD12 A17 GNT B17 Ground A48 Ground B48 AD10 A18 Ground B18 REQ A49 AD09 B49 Ground A19 PME B19 5 V I O A50 Key B50 Key A20 AD30 B20 AD31 A51 Key B51 Key A21 3 3 V B21 AD29 A52 C BE0 B52 AD08 A22 AD28 B22 Ground A53 3 3 V B53 AD07 A23 AD26 B23 AD27 A54 AD06 B54 3 3 V A24...

Page 61: ...1 Ground 12 Not connected 13 Ground 14 FDDS0 Drive Select A 15 Ground 16 Not connected 17 Not connected 18 FDDIR Stepper Motor Direction 19 Ground 20 FDSTEP Step Pulse 21 Ground 22 FDWD Write Data 23 Ground 24 FDWE Write Enable 25 Ground 26 FDTRK0 Track 0 27 Not connected 28 FDWPD Write Protect 29 Ground 30 FDRDATA Read Data 31 Ground 32 FDHEAD Side 1 Select 33 Ground 34 DSKCHG Diskette Change ...

Page 62: ...Data 13 15 Data 1 16 Data 14 17 Data 0 18 Data 15 19 Ground 20 Key 21 DDRQ0 DDRQ1 22 Ground 23 I O Write 24 Ground 25 I O Read 26 Ground 27 IOCHRDY 28 P_ALE Cable Select pull up 29 DDACK0 DDACK1 30 Ground 31 IRQ 14 IRQ 15 32 Reserved 33 DAG1 Address 1 34 Reserved 35 DAG0 Address 0 36 DAG2Address 2 37 Chip Select 1P Chip Select 1S 38 Chip Select 3P Chip Select 3S 39 Activity 40 Ground Note Signal n...

Page 63: ... I O connectors OM11035 A 1 15 2 1 2 9 1 1 2 10 D C B Item Description Reference Designator For more information see A Serial port B J1E2 Table 40 B Front panel USB J8B1 Table 41 C Front panel connector J8B2 Table 43 D Auxiliary front panel power LED J8A3 Table 42 Figure 11 External I O Connectors ...

Page 64: ...4 of the front panel connector Table 42 Auxiliary Front Panel Power LED Connector J8A3 Pin Signal In Out Description 1 HDR_BLNK_GRN Out Front panel green LED 2 No connect 3 HDR_BLNK_YEL Out Front panel yellow LED 2 8 3 2 Front Panel Connector This section describes the functions of the front panel connector Table 43 lists the signal names of the front panel connector Table 43 Front Panel Connector...

Page 65: ...ored LED Table 44 States for a Single colored Power LED LED State Description ACPI State Off Off S1 S3 S5 Steady Green Running S0 Blinking Green Running message waiting S0 Table 45 States for a Dual colored Power LED LED State Description ACPI State Off Off S5 Steady Green Running S0 Blinking Green Running message waiting S0 Steady Yellow Sleeping S1 S3 Blinking Yellow Sleeping message waiting S1 ...

Page 66: ...ays turn off the power and unplug the power cord from the computer before changing the jumper Otherwise the board could be damaged Figure 12 shows the location of the board s jumper blocks OM11036 B 4 6 1 3 J8A1 A 1 3 J8A2 A BIOS setup configuration jumper block B USB port 0 configuration jumper Figure 12 Location of the Jumper Blocks ...

Page 67: ... Configuration Normal 1 2 1 3 The BIOS uses current configuration information and passwords for booting Configure 2 3 1 3 After the POST runs Setup runs automatically The maintenance menu is displayed Recovery None 1 3 The BIOS attempts to recover the BIOS configuration A recovery medium is required 2 9 2 USB Port 0 Configuration Jumper Block This 6 pin jumper block allows rerouting of USB Port 0 ...

Page 68: ...s the mechanical form factor for the board Dimensions are given in inches millimeters The outer dimensions are 9 60 inches by 8 00 inches 243 84 x 203 20 millimeters Location of the I O connectors and mounting holes are in compliance with the microATX specification see Section 1 3 OM11037 6 50 165 10 1 50 38 10 0 55 13 97 2 60 66 04 8 80 223 52 5 20 132 08 9 05 229 87 0 00 0 80 20 32 0 00 6 10 154...

Page 69: ...uirements are described in the microATX specification NOTE A chassis independent I O shield designed to be compliant with the microATX chassis specification is available from Intel The actual punchouts may differ depending on the board manufacturing options 0 94 Ref 23 87 0 465 11 81 0 471 11 95 0 568 14 43 0 88 22 35 0 276 7 01 0 00 0 00 0 00 0 00 0 447 11 35 1 189 30 20 2 076 52 73 1 802 45 77 3...

Page 70: ...olors and 60 Hz refresh rate AC watts are measured with a typical 200 W supply nominal input voltage and frequency with a true RMS wattmeter at the line input NOTE Actual system power consumption depends upon system configuration The power supply should comply with the recommendations found in the ATX form factor specification Table 48 Power Usage DC Current at Mode AC Power 3 3 V 5 V 12 V 12 V 5 ...

Page 71: ...led devices installed and multiply by the standby current requirement for wake enabled devices 3 Add the PCI 2 2 slots with wake enabled devices installed and multiply by the standby current requirement for non wake enabled devices 4 Add all additional wake enabled devices and non wake enabled devices standby current requirements as applicable 5 Add all the required current totals from steps 1 thr...

Page 72: ...al names of the chassis fan connector Table 33 page 56 2 11 5 Power Supply Considerations CAUTION The 5 V standby line for the power supply must be capable of providing adequate 5 V standby current Failure to do so can damage the power supply The total amount of standby current required depends on the wake devices supported and manufacturing options Refer to Section 2 11 3 on page 71 for additiona...

Page 73: ...ations in Section 2 14 CAUTION The processor voltage regulator area item A in Figure 15 can reach a temperature of up to 85 o C in an open chassis System integrators should ensure that proper airflow is maintained in the voltage regulator circuit Failure to do so may result in damage to the voltage regulator circuit Figure 15 shows the locations of the localized high temperature zones OM11038 B D ...

Page 74: ...datasheets and processor specification updates Intel 82810E DC 133 GMCH 70 o C under bias Intel 82801BA ICH2 109 o C under bias For information about Refer to Intel Pentium III processor datasheets and specification updates Section 1 2 page 16 Intel Celeron processor datasheets and specification updates Section 1 2 page 16 2 13 Reliability The mean time between failures MTBF prediction is calculat...

Page 75: ...iance with U S and international safety and electromagnetic compatibility EMC regulations 2 15 1 Safety Regulations Table 53 lists the safety regulations the D810E2CA3 board complies with when correctly installed in a compatible host system Table 53 Safety Regulations Regulation Title UL 1950 CSA C22 2 No 950 3 rd edition Bi National Standard for Safety of Information Technology Equipment includin...

Page 76: ...al 2 15 3 Product Certification Markings Board Level The D810E2CA3 desktop board has the following product certification markings UL joint US Canada Recognized Component mark Consists of small c followed by a stylized backward UR and followed by a small US Includes adjacent UL file number for Intel desktop boards E210882 component side FCC Declaration of Conformity logo mark for Class B equipment ...

Page 77: ...memory contains the BIOS Setup program POST APM ACPI PCI auto configuration utility and Windows 98 ready Plug and Play This board supports system BIOS shadowing allowing the BIOS to execute from 64 bit onboard write protected DRAM The BIOS displays a message during POST identifying the type of BIOS and a revision code The initial production BIOS is identified as CA81030A 86A For information about ...

Page 78: ...gures them to optimize capacity and performance To take advantage of the high capacities typically available today hard drives are automatically configured for Logical Block Addressing LBA and to PIO Mode 3 or 4 depending on the capability of the drive You can override the auto configuration options by specifying manual configuration in the BIOS Setup program To use ATA 66 100 features the followi...

Page 79: ... as keyboards mice and hubs to be used even when the operating system s USB drivers are not yet available Legacy USB support is used to access the BIOS Setup program and to install an operating system that supports USB By default Legacy USB support is set to Enabled Legacy USB support operates as follows 1 When you apply power to the computer legacy support is disabled 2 POST begins 3 Legacy USB s...

Page 80: ...tolerant to prevent boot block corruption Updating the BIOS boot block separately Changing the language section of the BIOS Updating replaceable BIOS modules such as the video BIOS module Inserting a custom splash screen NOTE Review the instructions distributed with the upgrade utility before attempting a BIOS update For information about Refer to The Intel World Wide Web site Section 1 2 page 16 ...

Page 81: ...ire more time Two beeps and the end of activity in the diskette drive indicate successful BIOS recovery A series of continuous beeps indicates a failed BIOS recovery To create a BIOS recovery diskette a bootable diskette must be created and the BIOS update files copied to it BIOS upgrades and the Intel Flash Memory Update Utility are available from Intel Customer Support through the Intel World Wi...

Page 82: ...cification Section 1 3 page 16 3 8 2 Booting Without Attached Devices For use in embedded applications the BIOS has been designed so that after passing the POST the operating system loader is invoked even if the following devices are not present Video adapter Keyboard Mouse 3 9 Fast Booting Systems with Intel Rapid BIOS Boot Three factors affect system boot speed Selecting and configuring peripher...

Page 83: ...t where the system boots so quickly that the Intel logo screen or a custom logo splash screen will not be seen Monitors and hard disk drives with minimum initialization times can also contribute to a boot time that might be so fast that necessary logo screens and POST messages cannot be seen This boot time may be so fast that some drives might be not be initialized at all If this condition should ...

Page 84: ...ng the user password restricts who can boot the computer The password prompt will be displayed before the computer is booted If only the supervisor password is set the computer boots without asking for a password If both passwords are set the user can enter either password to boot the computer Table 55 shows the effects of setting the supervisor password and user password This table is for referen...

Page 85: ...er Boot Exit Table 56 lists the BIOS Setup program menu functions Table 56 BIOS Setup Program Menu Bar Maintenance Main Advanced Security Power Boot Exit Clears passwords and enables extended configuration mode Allocates resources for hardware components Configures advanced features available through the chipset Sets passwords and security features Configures power management features Selects boot...

Page 86: ...rity Power Boot Exit The menu shown in Table 58 is for clearing Setup passwords and enabling extended configuration mode Setup only displays this menu in configuration mode See Section 2 9 1 on page 67 for configuration mode setting information Table 58 Maintenance Menu Feature Options Description Clear All Passwords Yes default No Selecting Yes clears all passwords Clear BIS Credentials Yes defau...

Page 87: ...Extended Configuration Menu Feature Options Description Extended Configuration Default default User Defined Enables access to the extended memory configuration options Note If User Defined is selected the status will be displayed in the Advanced Menu as Extended Menu Used Memory Control SDRAM Auto Configuration Auto default User Defined Sets extended memory configuration options to auto or user de...

Page 88: ...sor Speed No options Displays processor speed System Bus Frequency No options Displays the system bus frequency Cache RAM No options Displays the size of second level cache Total Memory No options Displays the total amount of RAM on the board Bank 0 Bank 1 No options Displays the type of DIMM installed in each memory bank Language English default Espanol Deutsch Selects the current default languag...

Page 89: ... have been modified from the default setting PCI Configuration No options Allows access to PCI IRQ mapping Boot Configuration No options Configures Plug and Play and the Numlock key and resets configuration data When selected displays the Boot Settings Configuration submenu Peripheral Configuration No options Configures peripheral ports and devices When selected displays the Peripheral Configurati...

Page 90: ... 62 is used to configure the IRQ priority of PCI slots individually Table 62 PCI Configuration Submenu Feature Options Description PCI Slot1 IRQ Priority Auto default 9 10 11 Allows the user to map the PCI IRQ for slot 1 to a particular hardware interrupt PCI Slot2 IRQ Priority Auto default 9 10 11 Allows the user to map the PCI IRQ for slot 2 to a particular hardware interrupt PCI Slot3 IRQ Prior...

Page 91: ...ting configuration data and the power on state of the Numlock key Table 63 Boot Setting Configuration Submenu Feature Options Description Plug Play O S No default Yes Specifies if manual configuration is desired No lets the BIOS configure all devices This setting is appropriate when using a Plug and Play operating system Yes lets the operating system configure Plug and Play devices This option is ...

Page 92: ... the address 3F8h and the interrupt IRQ4 An asterisk displayed next to an address indicates a conflict with another device Base I O address 3F8 default 2F8 3E8 2E8 Specifies the base I O address for serial port A if Serial Port A is set to Enabled Interrupt IRQ 3 IRQ 4 default Specifies the interrupt for serial port A if Serial Port A is set to Enabled Serial port B Disabled Enabled Auto default C...

Page 93: ...tput Only operates in AT compatible mode Bi directional operates in PS 2 compatible mode EPP is Extended Parallel Port mode a high speed bi directional mode ECP is Enhanced Capabilities Port mode a high speed bi directional mode Base I O address 378 default 278 Specifies the base I O address for the parallel port Interrupt IRQ 5 IRQ 7 default Specifies the interrupt for the parallel port Audio Dev...

Page 94: ...he integrated IDE controller Primary enables only the Primary IDE Controller Secondary enables only the Secondary IDE Controller Both enables both IDE controllers Hard Disk Pre Delay Disabled default 3 Seconds 6 Seconds 9 Seconds 12 Seconds 15 Seconds 21 Seconds 30 Seconds Specifies the hard disk drive pre delay Primary IDE Master No options Reports type of connected IDE device When selected displ...

Page 95: ...menus Feature Options Description Drive Installed No options Displays the type of drive installed Type None User Auto default CD ROM ATAPI Removable Other ATAPI IDE Removable Specifies the IDE configuration mode for IDE devices User allows the user to change the LBA Mode Control Multi Sector Transfers PIO Mode and Ultra DMA settings Auto automatically sets the LBA Mode Control Multi Sector Transfe...

Page 96: ...nce Main Advanced Security Power Boot Exit Extended Configuration PCI Configuration Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration The submenu represented in Table 67 is used to configure the diskette drive Table 67 Diskette Configuration Submenu Feature Options Description Diskette Controller Disabled Enabled defaul...

Page 97: ...he submenu represented in Table 68 is used to configure the event logging features Table 68 Event Log Configuration Submenu Feature Options Description Event Log No options Indicates if there is space available in the event log Event Log Validity No options Indicates if the contents of the event log are valid View Event Log No options Displays the event log Clear All Event Logs No default Yes Clea...

Page 98: ...ration Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration The submenu represented in Table 69 is used to configure video features Table 69 Video Configuration Submenu Feature Options Description Primary Video Adapter AGP default PCI Allows the user to select between the onboard direct AGP graphics or the PCI add in graph...

Page 99: ...umeric characters Specifies the user password Clear User Password Note 1 No options Clears the user password User Access Level Note 2 Limited No Access View Only Full default Specifies the amount of user access to the Setup program Limited allows only limited fields to be changed No Access prevents user access View Only allows the user to view but not change the fields in the Setup program Full al...

Page 100: ...computer enters standby mode when APM power management is active Note Hard Drive Disabled Enabled default Enables or disables power management for hard disks during standby and suspend modes when APM power management is active Note ACPI Suspend State S1 State default S3 State Selects the suspend state the system will use when ACPI power management is active To enable an instantly available configu...

Page 101: ...pressed Last State restores the previous power state before power loss occurred On Modem Ring Stay Off default Power On Specifies how the computer responds to an incoming call on an installed modem when the power is off On LAN Stay Off default Power On Specifies how the computer responds to a LAN wakeup event when the power is off On PME Stay Off default Power On Specifies how the computer respond...

Page 102: ...in Table 73 is used to exit the Setup program saving changes and loading and saving defaults Table 73 Exit Menu Feature Description Exit Saving Changes Exits and saves the changes in CMOS SRAM Exit Discarding Changes Exits without saving any changes made in the Setup program Load Setup Defaults Loads the factory default values for all the Setup options Load Custom Defaults Loads the custom default...

Page 103: ...elected correctly A Drive Error No response from diskette drive Cache Memory Error An error occurred while testing L2 cache Cache memory may be bad CMOS Battery Low The battery may be losing power Replace the battery soon CMOS Display Type Wrong The display type is different than what has been stored in CMOS Check Setup to make sure type is correct CMOS Checksum Bad The CMOS checksum is incorrect ...

Page 104: ... be bad Serial presence detect SPD device data missing or inconclusive Do you wish to boot at 100 MHz bus speed Y N System memory does not appear to be SPD memory No Boot Device Available System did not find a boot device Off Board Parity Error A parity error occurred on an offboard card This error is followed by an address On Board Parity Error A parity error occurred in onboard memory This error...

Page 105: ...ode D3 Initialize chipset start memory refresh and determine memory size D4 Verify base memory D5 Initialization code to be copied to segment 0 and control to be transferred to segment 0 D6 Control is in segment 0 Used to check if in recovery mode and to verify main BIOS checksum If in recovery mode or if main BIOS checksum is wrong go to check point E0 for recovery Otherwise go to check point D7 ...

Page 106: ...ble 24 Do any setup before interrupt vector initialization 25 Interrupt vector initialization to begin Clear password if necessary 27 Next do any initialization before setting video mode 28 Set monochrome mode and color mode 2A Start initialization of different buses if present system static output devices See Section 5 3 for details of different buses 2B Give control for any setup required before...

Page 107: ...lete Ready to adjust displayed memory size for relocation shadow 51 Memory size display adjusted due to relocation shadow Memory test above 1 MB to follow 52 Memory testing initialization above 1 MB complete Ready to save memory size information 53 Memory size information is saved Processor registers are saved Ready to enter real mode 54 Shutdown successful processor in real mode Ready to disable ...

Page 108: ... control is complete Next give control to do any required processing after optional ROM returns control and enable external cache 99 Do any initialization required after optional ROM Test is over Ready to set up timer data area and printer base address 9A Return after setting timer and printer base address Ready to set the RS 232 base address 9B Returned after RS 232 base address Ready to do any i...

Page 109: ...nt buses initialization error messages 95 Initialization of different buses optional ROMs from C800 to start While control is inside the different bus routines additional checkpoints are output to port 80h as word values to identify the routines under execution In these word value checkpoints the low byte of the checkpoint is the system BIOS checkpoint from which the control is passed to the diffe...

Page 110: ...gh Byte Functions Value Description 0 Generic DIM Device Initialization Manager 1 Onboard system devices 2 ISA devices 3 EISA devices 4 ISA PnP devices 5 PCI devices 5 4 Speaker A 47 Ω inductive speaker is mounted on the board The speaker provides audible error code beep code information during the power on self test POST For information about Refer to The location of the onboard speaker Figure 1 ...

Page 111: ...n for that external device There are several POST routines that issue a POST terminal error and shut down the system if they fail Before shutting down the system the terminal error handler issues a beep code signifying the test point error writes the error to I O port 80h attempts to initialize the video and writes the error in the upper left corner of the screen using both monochrome and color ad...

Page 112: ...Intel Desktop Board D810E2CA3 Technical Product Specification 112 ...

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