Land Listing and Signal Descriptions
68
Datasheet
FERR#/PBE#
Output
FERR#/PBE# (floating point error/pending break event) is a
multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating-point
error and will be asserted when the processor detects an
unmasked floating-point error. When STPCLK# is not asserted,
FERR#/PBE# is similar to the ERROR# signal on the Intel 387
coprocessor, and is included for compatibility with systems using
MS-DOS*-type floating-point error reporting. When STPCLK# is
asserted, an assertion of FERR#/PBE# indicates that the
processor has a pending break event waiting for service. The
assertion of FERR#/PBE# indicates that the processor should be
returned to the Normal state. For additional information on the
pending break event functionality, including the identification of
support of the feature and enable/disable information, refer to
volume 3 of the
Intel Architecture Software Developer's Manual
and the
Intel Processor Identification and the CPUID Instruction
application note.
GTLREF[3:0]
Input
GTLREF[3:0] determine the signal reference level for GTL+ input
signals. GTLREF is used by the GTL+ receivers to determine if a
signal is a logical 0 or logical 1.
HIT#
HITM#
Input/
Output
Input/
Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
snoop operation results. Any FSB agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which
can be continued by reasserting HIT# and HITM# together.
IERR#
Output
IERR# (Internal Error) is asserted by a processor as the result of
an internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor FSB. This transaction
may optionally be converted to an external error signal (e.g., NMI)
by system core logic. The processor will keep IERR# asserted until
the assertion of RESET#.
This signal does not have on-die termination. Refer to
for termination requirements.
IGNNE#
Input
IGNNE# (Ignore Numeric Error) is asserted to the processor to
ignore a numeric error and continue to execute noncontrol
floating-point instructions. If IGNNE# is de-asserted, the
processor generates an exception on a noncontrol floating-point
instruction if a previous floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register 0 (CR0)
is set.
IGNNE# is an asynchronous signal. However, to ensure
recognition of this signal following an Input/Output write
instruction, it must be valid along with the TRDY# assertion of the
corresponding Input/Output Write bus transaction.
INIT#
Input
INIT# (Initialization), when asserted, resets integer registers
inside the processor without affecting its internal caches or
floating-point registers. The processor then begins execution at
the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests
during INIT# assertion. INIT# is an asynchronous signal and must
connect the appropriate pins/lands of all processor FSB agents.
If INIT# is sampled active on the active to inactive transition of
RESET#, then the processor executes its Built-in Self-Test (BIST).
Table 4-3.
Signal Description (Sheet 5 of 10)
Name
Type
Description
