Intel Core i7 Extreme Edition, Datasheet

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Datasheet 75
Signal Definitions
THERMTRIP# O Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level beyond which permanent silicon damage may
occur. Measurement of the temperature is accomplished through an internal
thermal sensor. Upon assertion of THERMTRIP#, the processor will shut off its
internal clocks (thus halting program execution) in an attempt to reduce the
processor junction temperature. To further protect the processor, its core voltage
(V
CC
), V
TTA
V
TTD
and V
DDQ
must be removed following the assertion of
THERMTRIP#. Once activated, THERMTRIP# remains latched until RESET# is
asserted. While the assertion of the RESET# signal may de-assert THERMTRIP#,
if the processor's junction temperature remains at or above the trip level,
THERMTRIP# will again be asserted after RESET# is de-asserted.
TMS I TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
TRST# I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be
driven low during power on Reset.
VCC I Power for processor core.
VCC_SENSE
VSS_SENSE O
O VCC_SENSE and VSS_SENSE provide an isolated, low impedance connection to
the processor core power and ground. They can be used to sense or measure
voltage near the silicon.
VCCPLL I Power for on-die PLL filter.
VCCPWRGOOD I VCCPWRGOOD (Power Good) is a processor input. The processor requires this
signal to be a clean indication that BCLK, V
CC
, V
CCPLL
, V
TTA
and V
TTD
supplies are
stable and within their specifications. 'Clean' implies that the signal will remain
low (capable of sinking leakage current), without glitches, from the time that the
power supplies are turned on until they come within specification. The signal
must then transition monotonically to a high state. VCCPWRGOOD can be driven
inactive at any time, but BCLK and power must again be stable before a
subsequent rising edge of VCCPWRGOOD. In addition at the time VCCPWRGOOD
is asserted RESET# must be active. The PWRGOOD signal must be supplied to
the processor. It should be driven high throughout boundary scan operation.
VDDPWRGOOD I VDDPWRGOOD is an input that indicates the V
DDQ
power supply is good. The
processor requires this signal to be a clean indication that the V
DDQ
power
supply is stable and within specifications. "Clean" implies that the signal will
remain low (capable of sinking leakage current), without glitches, from the time
that the Vddq supply is turned on until it comes within specification. The signals
must then transition monotonically to a high state.
The PwrGood signal must be supplied to the processor.
VID[7:6]
VID[5:3]/CSC[2:0]
VID[2:0]/MSID[2:0] I/O VID[7:0] (Voltage ID) are used to support automatic selection of power supply
voltages (V
CC
). The voltage supply for these signals must be valid before the VR
can supply V
CC
to the processor. Conversely, the VR output must be disabled
until the voltage supply for the VID signals become valid. The VR must supply
the voltage that is requested by the signals, or disable itself.
VID7 and VID6 should be tied separately to V
SS
using a 1 k Ω resistor during
reset (This value is latched on the rising edge of VTTPWRGOOD)
MSID[2:0] - MSID[2:0] is used to indicate to the processor whether the platform
supports a particular TDP. A processor will only boot if the MSID[2:0] pins are
strapped to the appropriate setting on the platform (see Table 2-2 for MSID
encodings). In addition, MSID protects the platform by preventing a higher
power processor from booting in a platform designed for lower power
processors.
CSC[2:0] - Current Sense Configuration bits, for ISENSE gain setting. This value
is latched on the rising edge of VTTPWRGOOD.
V
TTA
I Power for analog portion of the integrated memory controller, QPI and Shared
Cache.
V
TTD
I Power for the digital portion of the integrated memory controller, QPI and Shared
Cache.
Table 5-1. Signal Definitions (Sheet 3 of 4)
Name Type Description Notes