Intel BX80623G530 Specification Download Page 49 | Manualshive

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Specification Update

49

BJ93.

For A Single Logical Processor Package, HTT May be Set to Zero Even

Though The Package Reserves More Than One APIC ID

Problem:

When maximum number of addressable IDs for logical processors in this physical
package (CPUID.01H.EBX[23:16]) and maximum number of addressable IDs for
processor cores in the physical package, (CPUID.04H.EAX[31:26]) indicate more than
one reserved APIC ID, HTT (Multi-Threading, CPUID.01H.EDX[28]) should be set to
One. However, due to this erratum, it may be set to Zero.

Implication:

Software written expecting HTT to be Zero only when a single APIC ID is reserved for
the package may not function correctly.

Workaround:

It is possible for the BIOS to contain a workaround for this erratum.

Status:

For the steppings affected, see the Summary Tables of Changes.

BJ94.

LBR May Contain Incorrect Information When Using

FREEZE_LBRS_ON_PMI

Problem:

When FREEZE_LBRS_ON_PMI is enabled (bit 11 of IA32_DEBUGCTL MSR (1D9H) is
set), and a taken branch retires at the same time that a PMI (Performance Monitor
Interrupt) occurs, then under certain internal conditions the record at the top of the
LBR stack may contain an incorrect “From” address.

Implication:

When the LBRs are enabled with FREEZE_LRBS_ON_PMI, the “From” address at the top
of the LBR stack may be incorrect.

Workaround:

It is possible for the BIOS to contain a workaround for this erratum.

Status:

For the steppings affected, see the Summary Tables of Changes.

BJ95.

A First Level Data Cache Parity Error May Result in Unexpected

Behavior

Problem:

When a load occurs to a first level data cache line resulting in a parity error in close
proximity to other software accesses to the same cache line and other locked accesses
the processor may exhibit unexpected behavior.

Implication:

Due to this erratum, unpredictable system behavior may occur. Intel has not observed
this erratum with any commercially available system.

Workaround:

None identified.

Status:

For the steppings affected, see the Summary Tables of Changes.

BJ96.

Intel® Trusted Execution Technology ACM Revocation

Problem:

SINIT ACM 2nd_gen_i5_i7_SINIT_1.9.BIN or earlier are revoked and will not launch
with new processor configuration information.

Implication:

Due to this erratum, 2nd_gen_i5_i7_SINIT_1.9.BIN and earlier will be revoked.

Workaround:

It is possible for the BIOS to contain a workaround for this erratum. All Intel

®

TXT

enabled software must use SINIT ACM 2nd_gen_i5_i7_SINIT_1.9.BIN or later.

Status:

For the steppings affected, see the Summary Tables of Changes.

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Summary of Contents for BX80623G530

Page 1: ...rrata which may cause the product to deviate from published specifications Current characterized errata are available on request 2nd Generation Intel Core Processor Family Desktop Intel Pentium Processor Family Desktop and Intel Celeron Processor Family Desktop Specification Update June 2013 ...

Page 2: ...aunched or shipped They are never to be used as commercial names for products Also they are not intended to function as trademarks Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families Go to http www intel com products processor_number No computer system can provide absolute security un...

Page 3: ...ification Update 3 Contents Revision History 5 Preface 7 Summary Tables of Changes 9 Identification Information 16 Errata 23 Specification Changes 65 Specification Clarifications 66 Documentation Changes 67 ...

Page 4: ...4 Specification Update ...

Page 5: ...1 011 Added Erratum BJ96 Removed Erratum BJ73 November 2011 013 Skipped Revision 012 Updated Erratum BJ65 November 2011 014 Added G460 processor information November 2011 015 Added Errata BJ98 BJ99 and BJ100 January 2012 016 Added Errata BJ97 BJ101 BJ104 March 2012 017 Added Errata BJ105 BJ106 April 2012 018 Added Errata BJ107 BJ112 May 2012 019 Updated Processor Identification table to include th...

Page 6: ...6 Specification Update 027 Added Erratum BJ122 April 2013 028 Added SKUs Added Errata BJ123 BJ125 May 2013 029 Added Errata BJ126 BJ128 June 2013 Revision Description Date ...

Page 7: ...um Processor Family Desktop and Intel Celeron Processor Family Desktop Datasheet Volume 2 324642 003 Document Title Document Number Location AP 485 Intel Processor Identification and the CPUID Instruction http www intel com design processor applnots 241618 htm Intel 64 and IA 32 Architectures Software Developer s Manual Volume 1 Basic Architecture Intel 64 and IA 32 Architectures Software Develope...

Page 8: ...e of the specification Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a complex design situation These clarifications will be incorporated in any new release of the specification Documentation Changes include typos errors or omissions from the current published specifications These will be incorporated in any new release of ...

Page 9: ...es Stepping X Errata exists in the stepping indicated Specification Change or Clarification that applies to this stepping No mark or Blank box This erratum is fixed in listed stepping or specification change does not apply to listed stepping Page Page Page location of item in this document Status Doc Document change or update will be implemented Plan Fix This erratum may be fixed in a future stepp...

Page 10: ... Change BJ11 X X No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame BJ12 X X No Fix Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word BJ13 X X No Fix FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM BJ14 X X No Fix General Protection Fault GP for Instructions Greater than 15 Bytes May be Preempted BJ15 X X No Fix GP on Segment Select...

Page 11: ...alculated After an FP Access Which Wraps a 64 Kbyte Boundary in 16 Bit Code BJ40 X X No Fix Spurious Interrupts May be Generated From the Intel VT d Remap Engine BJ41 X X No Fix Fault Not Reported When Setting Reserved Bits of Intel VT d Queued Invalidation Descriptors BJ42 X X No Fix VPHMINPOSUW Instruction in Vex Format Does Not Signal UD When vex vvvv 1111b BJ43 X X No Fix LBR BTM or BTS Record...

Page 12: ... X No Fix TSC Deadline Not Armed While in APIC Legacy Mode BJ67 X X No Fix PCIe Upstream TCfgWr May Cause Unpredictable System Behavior BJ68 X X No Fix Processor May Fail to Acknowledge a TLP Request BJ69 X X No Fix Executing The GETSEC Instruction While Throttling May Result in a Processor Hang BJ70 X X No Fix PerfMon Event LOAD_HIT_PRE SW_PREFETCH May Overcount BJ71 X X No Fix Execution of FXSAV...

Page 13: ... May Result in Unexpected Behavior BJ96 X X No Fix Intel Trusted Execution Technology ACM Revocation BJ97 X X Plan Fix Programming PDIR And an Additional Precise PerfMon Event May Cause Unexpected PMI or PEBS Events BJ98 X X No Fix Performance Monitoring May Overcount Some Events During Debugging BJ99 X X No Fix LTR Message is Not Treated as an Unsupported Request BJ100 X X No Fix Use of VMASKMOV ...

Page 14: ... X X No Fix Specific Graphics Blitter Instructions May Result in Unpredictable Graphics Controller Behavior BJ121 X X No Fix IA32_MC5_CTL2 is Not Cleared by a Warm Reset BJ122 X X Plan Fix Performance Monitor Counters May Produce Incorrect Results BJ123 X X No Fix The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated After a UC Error is Logged BJ124 X X No Fix Spurious Intel VT...

Page 15: ... Specification Update 15 Documentation Changes Number DOCUMENTATION CHANGES BJ1 On Demand Clock Modulation Feature Clarification ...

Page 16: ... the processor stepping ID number in the CPUID information When EAX is initialized to a value of 1 the CPUID instruction returns the Extended Family Extended Model Processor Type Family Code Model Number and Stepping ID value in the EAX register Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register Cache and TLB descriptor...

Page 17: ... Notes SR00C i7 2600K D 2 000206a7h 3 4 1333 850 4 core 3 5 3 core 3 6 2 core 3 7 1 core 3 8 8 2 4 6 SR00B i7 2600 D 2 000206a7h 3 4 1333 850 4 core 3 5 3 core 3 6 2 core 3 7 1 core 3 8 8 2 3 4 5 6 SR00E i7 2600S D 2 000206a7h 2 8 1333 850 4 core 2 9 3 core 3 3 2 core 3 7 1 core 3 8 8 2 3 4 5 6 SR0DG i7 2700K D 2 000206a7h 3 5 1333 850 4 core N A 3 core N A 2 core N A 1 core 3 9 8 2 4 6 SR008 i5 2...

Page 18: ...2 000206a7h 2 8 1333 850 4 core 2 9 3 core 3 0 2 core 3 0 1 core 3 1 6 4 6 SR0G1 i5 2450P D 2 000206a7h 3 2 1333 N A 4 core N A 3 core N A 2 core N A 1 core 3 5 6 4 6 SR0G2 i5 2380P D 2 000206a7h 3 1 1333 N A 4 core N A 3 core N A 2 core N A 1 core 3 4 6 4 6 SR0QH i5 2550K D 2 000206a7h 3 4 1333 N A 4 core N A 3 core N A 2 core N A 1 core 3 8 6 4 6 SR05C i3 2100 Q 0 000206a7h 3 1 1333 850 N A 3 2 ...

Page 19: ... 850 N A 3 4 SR05U G630T Q 0 000206a7h 2 3 1066 650 N A 3 4 SR05R G620 Q 0 000206a7h 2 6 1066 850 N A 3 4 SR05T G620T Q 0 000206a7h 2 2 1066 650 N A 3 4 SR0GR G460 Q 0 000206a7h 1 8 1066 650 N A 1 5 4 SR0BY G440 Q 0 000206a7h 1 6 1066 650 N A 1 4 SR061 G550 Q 0 000206a7h 2 6 1066 850 N A 2 4 SR05L G540T Q 0 000206a7h 2 1 1066 650 N A 2 4 SR05H G530 Q 0 000206a7h 2 4 1066 850 N A 2 4 SR05K G530T Q ...

Page 20: ...per s Manual the use of MOV SS POP SS in conjunction with MOV r e SP r e BP will avoid the failure since the MOV r e SP r e BP will not generate a floating point exception Developers of debug tools should be aware of the potential incorrect debug event signaling created by this erratum Status For the steppings affected see the Summary Tables of Changes BJ2 APIC Error Received Illegal Vector May be...

Page 21: ...riers software may see load operations execute out of order Implication Memory ordering may be violated Intel has not observed this erratum with any commercially available software Workaround Software should ensure pages are not being actively used before requesting their memory type be changed Status For the steppings affected see the Summary Tables of Changes BJ6 Code Segment Limit Canonical Fau...

Page 22: ... breakpoint enable flags are disabled DR7 G0 G3 and DR7 L0 L3 the DR6 B0 B3 flags may be incorrect Implication The debug exception DR6 B0 B3 flags may be incorrect for the load if the corresponding breakpoint enable flag in DR7 is disabled Workaround None identified Status For the steppings affected see the Summary Tables of Changes BJ9 DR6 B0 B3 May Not Report All Breakpoints Matched When a MOV P...

Page 23: ...n will produce the same results as if it had initially completed without fault or VM exit Workaround If the handler of the affected events inspects the arithmetic portion of the saved EFLAGS value then system software should perform a synchronized paging structure modification and TLB invalidation Status For the steppings affected see the Summary Tables of Changes BJ11 Fault on ENTER Instruction M...

Page 24: ...o this erratum if 1 A performance counter overflowed before an SMI 2 A PEBS record has not yet been generated because another count of the event has not occurred 3 The monitored event occurs during SMM then a PEBS record will be saved after the next RSM instruction When FREEZE_WHILE_SMM is set a PEBS should not be generated until the event occurs outside of SMM Implication A PEBS record may be sav...

Page 25: ...tart an I O instruction if the platform has not been configured to generate a synchronous SMI for the recorded I O port address Status For the steppings affected see the Summary Tables of Changes BJ17 IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception Problem In IA 32e mode it is possible to get an Alignment Check Exception AC on the IRET instruction even though alignm...

Page 26: ...can incorrectly set the Overflow bit 62 in the MCi_Status register A DTLB error is indicated by MCA error code bits 15 0 appearing as binary value 000x 0000 0001 0100 in the MCi_Status register Implication Due to this erratum the Overflow bit in the MCi_Status register may not be an accurate indication of multiple occurrences of DTLB errors There is no other impact to normal processor functionalit...

Page 27: ...toring counter is configured for PEBS Precise Event Based Sampling overflows of the counter can result in storage of a PEBS record in the PEBS buffer Due to this erratum if the overflow occurs during probe mode it may be ignored and a new PEBS record may not be added to the PEBS buffer Implication Due to this erratum the PEBS buffer may not be updated by overflows that occur during probe mode Work...

Page 28: ...led Status For the steppings affected see the Summary Tables of Changes BJ26 Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data Structures Problem Bits 53 50 of the IA32_VMX_BASIC MSR report the memory type that the processor uses to access the VMCS and data structures referenced by pointers in the VMCS Due to this erratum a VMX access to the VMCS or referenced data struct...

Page 29: ... May Be Delayed by One Instruction Problem If VM entry is executed with the NMI window exiting VM execution control set to 1 a VM exit with exit reason NMI window should occur before execution of any instruction if there is no virtual NMI blocking no blocking of events by MOV SS and no blocking of events by STI If VM entry is made with no virtual NMI blocking but with blocking of events by either ...

Page 30: ...request will be dropped and a completion will be sent with the UR Unsupported Request completion status This completion according to the PCIe specification should indicate a byte count of 4 Due to this erratum the byte count is set to the same byte count as the offending request Implication The processor response to an unsupported PCIe access may not fully comply to the PCIe specification Workarou...

Page 31: ...ified Status For the steppings affected see the Summary Tables of Changes BJ36 Incorrect Address Computed For Last Byte of FXSAVE FXRSTOR or XSAVE XRSTOR Image Leads to Partial Memory Update Problem A partial memory state save of the FXSAVE or XSAVE image or a partial memory state restore of the FXRSTOR or XRSTOR image may occur if a memory address exceeds the 64KB limit while the processor is ope...

Page 32: ...e operand associated with the last non control FP instruction executed by the processor If an 80 bit FP access load or store occurs in a 16 bit mode other than protected mode in which case the access will produce a segment limit violation the memory access wraps a 64 Kbyte boundary and the FP environment is subsequently saved the value contained in the FP Data Operand Pointer may be incorrect Impl...

Page 33: ...reserved instruction VPHMINPOSUW with vex vvvv 1111b Implication Executing VPHMINPOSUW with vex vvvv 1111b results in the same behavior as executing with vex vvvv 1111b Workaround Software should not use VPHMINPOSUW with vex vvvv 1111b in order to ensure future compatibility Status For the steppings affected see the Summary Tables of Changes BJ43 LBR BTM or BTS Records May have Incorrect Branch Fr...

Page 34: ...id accessing unsupported fields in a VMCS Status For the steppings affected see the Summary Tables of Changes BJ45 Clock Modulation Duty Cycle Cannot be Programmed to 6 25 Problem When programming field T_STATE_REQ of the IA32_CLOCK_MODULATION MSR 19AH bits 3 0 to 0001 the actual clock modulation duty cycle will be 12 5 instead of the expected 6 25 ratio Implication Due to this erratum it is not p...

Page 35: ...tate via the retrain link configuration bit in the Link Control register Bus 0 Device 1 Functions 0 1 2 and Device 6 Function 0 Offset B0H bit 5 then the root port may not mask the receiver or bad DLLP Data Link Layer Packet errors as expected These correctable errors should only be considered valid during PCIe configuration and L0 but not L0s This causes the processor to falsely report correctabl...

Page 36: ...by graphics from certain memory ranges may cause memory reads to be stalled resulting in a system hang The following physical page 4K addresses cannot be assigned to Processor Graphics 00_2005_0xxx 00_2013_0xxx 00_2013_8xxx and 00_4000_4xxx Implication Due to this erratum accesses by the graphics engine to the defined memory ranges may cause memory reads to be stalled resulting in a system hang Wo...

Page 37: ...d see the Summary Tables of Changes BJ55 Instruction Fetch May Cause Machine Check if Page Size and Memory Type Was Changed Without Invalidation Problem This erratum may cause a machine check error IA32_MCi_STATUS MCACOD 0150H on the fetch of an instruction that crosses a 4 KByte address boundary It applies only if 1 the 4 KByte linear region on which the instruction begins is originally translate...

Page 38: ...ected see the Summary Tables of Changes BJ58 Performance Counter Overflow Indication May Cause Undesired Behavior Problem Under certain conditions listed below when a performance counter overflows its overflow indication may remain set indefinitely This erratum affects the general purpose performance counters IA32_PMC 0 7 and the fixed function performance counters IA32_FIXED_CTR 0 2 The erratum m...

Page 39: ... over twice the value specified in the Intel 64 and IA 32 Architectures Optimization Reference Manual Implication While typical exit latencies are not impacted the worst case core C state exit latency may be over twice the value specified in the Intel 64 and IA 32 Architectures Optimization Reference Manual and may lead to a delay in servicing interrupts Intel has not observed any system failures ...

Page 40: ...rratum Interrupts blocked in this way produce a remapping fault with fault reason 26H Status For the steppings affected see the Summary Tables of Changes BJ63 PCIe Link Speed May Not Change From 5 0 GT s to 2 5 GT s Problem If a PCI Express device changes its supported PCIe link speed from 5 0 GT s to 2 5 GT s without initiating a speed change request and subsequently the L1 power management mode ...

Page 41: ...are Developer s Manual for recommendations for software treatment of asynchronous paging structure updates Status For the steppings affected see the Summary Tables of Changes BJ66 TSC Deadline Not Armed While in APIC Legacy Mode Problem Under specific timing conditions when in Legacy APIC Mode writing to IA32_TSC_DEADLINE MSR 6E0H may fail to arm the TSC Deadline Time Stamp Counter Deadline event ...

Page 42: ...cution of GETSEC instruction Intel has not been observed this erratum with any commercially available software Workaround None Identified Status For the steppings affected see the Summary Tables of Changes BJ70 PerfMon Event LOAD_HIT_PRE SW_PREFETCH May Overcount Problem PerfMon event LOAD_HIT_PRE SW_PREFETCH event 4CH umask 01H should count load instructions hitting an ongoing software cache fill...

Page 43: ...tware can avoid this by Avoid using Freeze PerfMon on PMI bit Enable only one fixed counter at a time when using Freeze PerfMon on PMI Status For the steppings affected see the Summary Tables of Changes BJ75 GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch Instructions Problem When a 2 byte opcode of a conditional branch opcodes 0F8xH for any value of x instruction resides in...

Page 44: ...karound It is possible for the BIOS to contain a workaround for this erratum Status For the steppings affected see the Summary Tables of Changes BJ79 RC6 Entry Can be Blocked by Asynchronous Intel VT d Flows Problem The graphics Command Streamer can get into a state that will effectively inhibit graphic RC6 Render C6 power management state entry until render reset occurs Any asynchronous Intel VT ...

Page 45: ...eset Problem Under certain conditions when there is no PCIe device present the status of Presence Detect State bit SLOTSTS Device 1 Function 0 1 2 Offset BAH bit 6 and or Device 6 Function 0 Offset BAH bit 6 may not be accurate after a warm reset Implication The Presence Detect State bit may incorrectly report a PCIe device is present even though no device is actually present which may result in a...

Page 46: ...Workaround It is possible for the BIOS to contain a workaround for this erratum Status For the steppings affected see the Summary Tables of Changes BJ87 Interrupt From Local APIC Timer May Not Be Detectable While Being Delivered Problem If the local APIC timer s CCR current count register is 0 software should be able to determine whether a previously generated timer interrupt is being delivered by...

Page 47: ...fault that indicates that there is no translation for the page Intel has not observed this erratum with any commercially available software Workaround None identified Status For the steppings affected see the Summary Tables of Changes BJ89 A PCIe Device That Initially Transmits Minimal Posted Data Credits May Cause a System Hang Problem Under certain conditions if a PCIe device that initially tran...

Page 48: ...ents software may count the same event on both threads of the same physical core and at post processing stage sum up the two values to get the core s net value Status For the steppings affected see the Summary Tables of Changes BJ92 PDIR May Not Function Properly With FREEZE_PERFMON_ON_PMI Problem When the PDIR Precise Distribution for Instructions Retired mechanism is activated INST_RETIRED ALL e...

Page 49: ...t From address Implication When the LBRs are enabled with FREEZE_LRBS_ON_PMI the From address at the top of the LBR stack may be incorrect Workaround It is possible for the BIOS to contain a workaround for this erratum Status For the steppings affected see the Summary Tables of Changes BJ95 A First Level Data Cache Parity Error May Result in Unexpected Behavior Problem When a load occurs to a firs...

Page 50: ...TR 3 0 BR_INST_RETIRED BR_MISP_RETIRED FP_ASSIST FP_ASSIST INST_RETIRED MACHINE_CLEARS MEM_LOAD_UOPS_LLC_HIT_RETIRED MEM_LOAD_UOPS_MISC_RETIRED LLC_MISS MEM_LOAD_UOPS_RETIRED MEM_TRANS_RETIRED MEM_UOPS_RETIRED OTHER_ASSISTS ROB_MISC_EVENTS LBR_INSERTS UOPS_RETIRED Any of the globally enabled via IA32_CR_EMON_PERF_GLOBAL_CTRL counters may overcount certain events when a disabled breakpoint conditio...

Page 51: ... see the Summary Tables of Changes BJ102 XSAVEOPT May Fail to Save Some State after Transitions Into or Out of STM Problem The XSAVEOPT instruction may optimize performance by not saving state that has not been modified since the last execution of XRSTOR This optimization should occur only if the executions of XSAVEOPT and XRSTOR are either both or neither in SMM system management mode Due to this...

Page 52: ...SCOD of 119H Workaround None identified Status For the steppings affected see the Summary Tables of Changes BJ105 MSR_PKG_Cx_RESIDENCY MSRs May Not be Accurate Problem If the processor is in a package C state for an extended period of time greater than 40 seconds with no wake events the value in the MSR_PKG_C 2 3 6 7 _RESIDENCY MSRs 60DH and 3F8H 3FAH will not be accurate Implication Utilities tha...

Page 53: ... on counter configuration Implication Successive Fixed Counter overflows may be discarded when Freeze PerfMon on PMI is used Workaround Software can avoid this by Avoid using Freeze PerfMon on PMI bit Enable only one fixed counter at a time when using Freeze PerfMon on PMI Status For the steppings affected see the Summary Tables of Changes BJ110 Execution of FXSAVE or FXRSTOR With the VEX Prefix M...

Page 54: ...ll cause a UD Implication Unexpected UDs will be seen when the VEX L bit is set to 1 with VCVTSS2SI VCVTSD2SI VCVTTSS2SI and VCVTTSD2SI instructions Workaround Software should ensure that the VEX L bit is set to 0 for all scalar instructions Status For the steppings affected see the Summary Tables of Changes BJ114 MCI_ADDR May be Incorrect For Cache Parity Errors Problem In cases when a WBINVD ins...

Page 55: ...nd within the published power and thermal specifications Workaround None identified Status For the steppings affected see the Summary Tables of Changes BJ117 The Processor May Not Properly Execute Code Modified Using A Floating Point Store Problem Under complex internal conditions a floating point store used to modify the next sequential instruction may result in the old instruction being executed...

Page 56: ... the steppings affected see the Summary Tables of Changes BJ120 Specific Graphics Blitter Instructions May Result in Unpredictable Graphics Controller Behavior Problem Specific source copy blitter instructions in Intel HD Graphics 2000 and 3000 Processor may result in unpredictable behavior when a blit source and destination overlap Implication Due to this erratum the processor may exhibit unpredi...

Page 57: ...m When a UC uncorrected error is logged in the IA32_MC0_STATUS MSR 401H corrected errors will continue to update the lower 14 bits bits 51 38 of the Corrected Error Count Due to this erratum the sticky count overflow bit bit 52 of the Corrected Error Count will not get updated after a UC error is logged Implication The Corrected Error Count Overflow indication will be lost if the overflow occurs a...

Page 58: ...eturns to 32 bit paging without changing CR3 Intel has not observed this erratum with any commercially available software Workaround Software that has executed in 64 bit mode should reload CR3 with a 32 bit value before returning to 32 bit paging Status For the steppings affected see the Summary Tables of Changes BJ127 EPT Violations May Report Bits 11 0 of Guest Linear Address Incorrectly Problem...

Page 59: ...9 Implication Software that uses the value reported in IA32_VMX_VMCS_ENUM 9 1 to read and write all VMCS fields may omit one field Workaround None identified Status For the steppings affected see the Summary Tables of Changes ...

Page 60: ...cture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Prog...

Page 61: ...itectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide There are no ne...

Page 62: ...On Demand Clock Modulation Feature Clarification Software Controlled Clock Modulation section of the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide will be modified to differentiate On demand clock modulation feature on different processors The clarification will state For Hyper Threading Technology enabled processors the IA32_CLOCK_MODULATION regis...

Page 63: ...sors That Resolve to Higher Performance Setting of Conflicting Duty Cycle Requests DisplayFamily_Display Model DisplayFamily_Display Model DisplayFamily_Display Model DisplayFamily_Display Model 0F_xx 06_1C 06_1A 06_1E 06_1F 06_25 06_26 06_27 06_2C 06_2E 06_2F 06_35 06_36 ...

Page 64: ...64 Specification Update ...

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