Intel
®
Core™ 2 Duo Processor and Intel
®
Core™ Duo Processor with Intel
®
E7520 Chipset
Development Kit
Intel
®
Core™ 2 Duo Processor and Intel
®
Core™ Duo Processor with Intel
®
E7520 Chipset Development Kit
User’s Manual
January 2007
40
Order Number: 316068-001US
4.2.4
S3 State
This state is called Suspend to RAM (STR). The system context is maintained in system
DRAM, but power is shut off to non-critical circuits. Memory is retained, and refreshes
continue. All clocks stop except the RTC. S3 is entered when the I/O controller asserts
the SLP_S3# signal to downstream circuitry to control 1.8 V power plane switching.
Power must be switched from the normal 1.8 V rail to standby 1.8 V, because the
450 W SSI 12 V power supply does not directly supply a standby 1.8 V rail. The
sequence to enter Suspend to RAM is as follows:
1. The OS and BIOS prepare for S3 sleep state.
2. The OS sets the appropriate sleep bits in the I/O controller.
3. The I/O controller drives STPCLK to the processor.
4. The processor respond with a Stop-Grant cycle, passed over hub interface by MCH.
5. The I/O controller indicates an S3 (STR) sleep mode to the MCH via Hub Interface
A.
6. The MCH puts DDR memory into the self-refresh mode.
7. The MCH drives DDR CMDCLK differential pairs and all DDR outputs low.
8. The MCH drives a completion message via Hub Interface A to the I/O controller.
9. The I/O controller turns off all voltage rails (except Standby 5 V) from the main
power supply by asserting the SLP_S3_N signal.
When in the S3 state, only the standby 5 V rail is available from the power supply. The
board uses this standby source to generate 1.8 V standby rail to power the DIMMs.
The asserted SLP_S3_N signal also controls the logic to switch the DIMM power source
from main 1.8 V to standby 1.8 V.
4.2.5
S4 State
This state is not supported.
4.2.6
S5 State
This state is the normal off state whether entered through the power button or soft off.
All power is shut off except for the logic required to restart. The system remains in the
S5 state only while the power supply is plugged into the electrical outlet. If the power
supply is unplugged, this is considered a mechanical off or G3.
4.2.7
Wake-Up Events
The types of wake-up events and wake-up latencies are related to the actual power
rails available to the system in a particular sleep state, as well as to the location in
which the system context is stored. Regardless of the sleep state, wake on the power
button is always supported except in a mechanical off situation. When in a sleep state,
the system complies with the PCI specification by supplying the optional 3.3 V standby
voltage to each PCI slot as well as the PME# signal. This enables any compliant PCI
card to wake up the system from any supported sleep state except mechanical off.
4.2.8
Wake from S1 Sleep State
During S1 the system is fully powered, permitting support for PCI Express* Wake and
Wake on PCI PME#.
4.2.9
Wake from S3 State
Keyboard press or mouse movement is used to wake from S3.
