Intel BX80532PG3200D Datasheet Download

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Datasheet

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Summary of Contents for BX80532PG3200D

Page 1: ...Document Number 322875 001EN Intel Pentium Processor on 45 nm Process Datasheet For Platforms Based on Mobile Intel 4 Series Express Chipset Family October 2009...

Page 2: ...ns Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order 64 bit comp...

Page 3: ...FSB Frequency Select Signals BSEL 2 0 25 3 7 FSB Signal Groups 26 3 8 CMOS Signals 27 3 9 Maximum Ratings 27 3 10 Processor DC Specifications 28 4 Package Mechanical Specifications and Pin Informatio...

Page 4: ...Ratings 27 6 Voltage and Current Specifications for the Pentium Processors 29 7 AGTL Signal Group DC Specifications 31 8 CMOS Signal Group DC Specifications 32 9 Open Drain Signal Group DC Specificat...

Page 5: ...Datasheet 5 Revision History Document Number Revision Number Description Date 322875 001 Initial Draft October 2009...

Page 6: ...6 Datasheet...

Page 7: ...c Execution Supports L1 cache to cache C2C transfer On die primary 32 KB instruction cache and 32 KB write back data cache in each core The processor have an on die 1 MB second level shared cache with...

Page 8: ...pon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packa...

Page 9: ...Chipset Family Datasheet 320122 Mobile Intel 4 Series Express Chipset Family Specification Update 320123 Intel I O Controller Hub 9 ICH9 I O Controller Hub 9M ICH9M Datasheet 316972 Intel I O Controll...

Page 10: ...Introduction 10 Datasheet...

Page 11: ..._BLK register block mapped in the processor s I O address space The P_LVLx I O reads are converted to equivalent MWAIT C state requests inside the processor and do not directly result in I O reads on...

Page 12: ...ak MWAIT C1 C1 Auto Halt Halt break HLT instruction STPCLK de asserted STPCLK asserted STPCLK de asserted STPCLK asserted STPCLK de asserted STPCLK asserted halt break A20M transition INIT INTR NMI PR...

Page 13: ...erdown state See the Intel 64 and IA 32 Architectures Software Developer s Manuals Volume 3A 3B System Programmer s Guide for more information The system can generate a STPCLK while the processor is i...

Page 14: ...the processor core flushes the contents of its L1 caches into the processor s L2 cache Except for the caches the processor core maintains all its architectural states in the C3 state The Monitor rema...

Page 15: ...r returns to the Stop Grant state once the snoop has been serviced or the interrupt has been latched 2 1 2 4 Sleep State The Sleep state is a low power state in which the processor maintains its conte...

Page 16: ...toggling BCLK within 10 BCLK periods To re enter the Sleep state the DPSLP pin must be deasserted BCLK can be re started after DPSLP deassertion as described above A period of 15 microseconds to allo...

Page 17: ...ble MSR The processor waits for a fixed time period If the die temperature is down to acceptable levels an up transition to the previous frequency and voltage point occurs An interrupt is generated fo...

Page 18: ...package low power states to enhanced package low power states Caution Extended Stop Grant must be enabled via the BIOS for the processor to remain within specification As processor technology changes...

Page 19: ...I signal that is asserted when the processor is in a reduced power consumption state PSI can be used to improve intermediate and light load efficiency of the voltage regulator resulting in platform po...

Page 20: ...Low Power Features 20 Datasheet...

Page 21: ...ken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in the tables in Section 3 10 Failure to do so can result in timing violations or...

Page 22: ...0 0 1 0 1 4750 0 0 0 0 0 1 1 1 4625 0 0 0 0 1 0 0 1 4500 0 0 0 0 1 0 1 1 4375 0 0 0 0 1 1 0 1 4250 0 0 0 0 1 1 1 1 4125 0 0 0 1 0 0 0 1 4000 0 0 0 1 0 0 1 1 3875 0 0 0 1 0 1 0 1 3750 0 0 0 1 0 1 1 1...

Page 23: ...1 1 1 1 0 0 0 7500 0 1 1 1 1 0 1 0 7375 0 1 1 1 1 1 0 0 7250 0 1 1 1 1 1 1 0 7125 1 0 0 0 0 0 0 0 7000 1 0 0 0 0 0 1 0 6875 1 0 0 0 0 1 0 0 6750 1 0 0 0 0 1 1 0 6625 1 0 0 0 1 0 0 0 6500 1 0 0 0 1 0 1...

Page 24: ...1 0 1 0 0 0 0 2000 1 1 0 1 0 0 1 0 1875 1 1 0 1 0 1 0 0 1750 1 1 0 1 0 1 1 0 1625 1 1 0 1 1 0 0 0 1500 1 1 0 1 1 0 1 0 1375 1 1 0 1 1 1 0 0 1250 1 1 0 1 1 1 1 0 1125 1 1 1 0 0 0 0 0 1000 1 1 1 0 0 0 1...

Page 25: ...ted Connection of these pins to VCC VSS or to any other signal including each other can result in component malfunction or incompatibility with future processors See Section 4 2 for a pin listing of t...

Page 26: ...als are common clock source synchronous and asynchronous NOTES See next page Table 4 FSB Pin Groups Signal Group Type Signals1 AGTL Common Clock Input Synchronous to BCLK 1 0 BPRI DEFER PREQ 5 RESET R...

Page 27: ...ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these...

Page 28: ...rocessor 6 For Intel Pentium processors in 22x22 mm package 3 10 Processor DC Specifications The processor DC specifications in this section are defined at the processor core pads unless noted otherwi...

Page 29: ...25 1 5 1 575 V ICCDES ICC for Processors Recommended Design Target 47 A 10 ICC ICC for Processors Processor Number Core Frequency Voltage T4500 T4400 T4300 T4200 2 3 GHz VCCHFM 2 2 GHz VCCHFM 2 1 GHz...

Page 30: ...rboard 6 VCC BOOT tolerance shown in Figure 7 and Figure 8 7 Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal VCC Not 100 te...

Page 31: ...ff Vin between 0 and VCCP 9 Cpad includes die capacitance only No package parasitics are included 10 This is the external resistor on the comp pins 11 On die termination resistance measured at 0 33 VC...

Page 32: ...to VCCP 4 For Vin between 0 V and VOH 5 Cpad includes die capacitance only No package parasitics are included Table 8 CMOS Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Notes1 VCCP...

Page 33: ...nical package pressure specifications are in a direction normal to the surface of the processor This protects the processor die from fracture risk due to uneven die pressure distribution under tilt st...

Page 34: ...Micro FCPGA Processor Package Drawing Sheet 1 of 2 TOP VIEW FRONT VIEW SIDE VIEW BOTTOM VIEW 0 1 0102 3 4 5 6 7 P 0 65 MAX 0 65 MAX 0 37 MAX 2 03 0 08 1 2 4 1 10 2 2 1 0 1 2 1 1 0 0 0 1 10 1 1 0 0 7 2...

Page 35: ...re 5 1 MB Die Micro FCPGA Processor Package Drawing Sheet 2 of 2 TOP VIEW SIDE VIEW BOTTOM VIEW CORNER KEEP OUT ZONE 4X EDGE KEEP OUT ZONE 4X 4X 7 00 4X 5 00 4X 7 00 13 97 6 985 13 97 6 985 1 625 1 5...

Page 36: ...DPRSTP VSS VCC VSS VCC VCC VSS VCC VCC E F BR0 VSS RS 0 RS 1 VSS RSVD VCC VSS VCC VCC VSS VCC VSS F G VSS TRDY RS 2 VSS BPRI HIT G H ADS REQ 1 VSS LOCK DEFER VSS H J A 9 VSS REQ 3 A 3 VSS VCCP J K VSS...

Page 37: ...10 VSS DSTBN 0 J K VCCP D 14 VSS D 8 D 17 VSS K L VSS D 22 D 20 VSS D 29 DSTBN 1 L M VCCP VSS D 23 D 21 VSS DSTBP 1 M N VCCP D 16 VSS DINV 1 D 31 VSS N P VSS D 26 D 25 VSS D 24 D 18 P R VCCP VSS D 19...

Page 38: ...nput Output A 9 J1 Source Synch Input Output A 10 N3 Source Synch Input Output A 11 P5 Source Synch Input Output A 12 P2 Source Synch Input Output A 13 L2 Source Synch Input Output A 14 P4 Source Sync...

Page 39: ...3 Source Synch Input Output A 33 AA4 Source Synch Input Output A 34 AB2 Source Synch Input Output A 35 AA3 Source Synch Input Output A20M A6 CMOS Input ADS H1 Common Clock Input Output ADSTB 0 M1 Sour...

Page 40: ...E22 Source Synch Input Output D 1 F24 Source Synch Input Output D 2 E26 Source Synch Input Output D 3 G22 Source Synch Input Output D 4 F23 Source Synch Input Output D 5 G25 Source Synch Input Output...

Page 41: ...22 Source Synch Input Output D 23 M23 Source Synch Input Output D 24 P25 Source Synch Input Output D 25 P23 Source Synch Input Output D 26 P22 Source Synch Input Output D 27 T24 Source Synch Input Out...

Page 42: ...rce Synch Input Output D 45 AA23 Source Synch Input Output D 46 AA24 Source Synch Input Output D 47 AB25 Source Synch Input Output D 48 AE24 Source Synch Input Output D 49 AD24 Source Synch Input Outp...

Page 43: ...E25 Source Synch Input Output DSTBP 0 H26 Source Synch Input Output DSTBP 1 M26 Source Synch Input Output Table 10 Pin Name Listing Pin Name Pin Signal Buffer Type Direction DSTBP 2 AA26 Source Synch...

Page 44: ...Output THRMDA A24 Power Other THRMDC B25 Power Other TMS AB5 CMOS Input TRDY G2 Common Clock Input TRST AB6 CMOS Input VCC A7 Power Other Table 10 Pin Name Listing Pin Name Pin Signal Buffer Type Dir...

Page 45: ...Other VCC AD18 Power Other VCC AE9 Power Other VCC AE10 Power Other Table 10 Pin Name Listing Pin Name Pin Signal Buffer Type Direction VCC AE12 Power Other VCC AE13 Power Other VCC AE15 Power Other...

Page 46: ...VCC E13 Power Other VCC E15 Power Other VCC E17 Power Other Table 10 Pin Name Listing Pin Name Pin Signal Buffer Type Direction VCC E18 Power Other VCC E20 Power Other VCC F7 Power Other VCC F9 Power...

Page 47: ...er Other VSS A16 Power Other VSS A19 Power Other VSS A23 Power Other VSS A25 Power Other Table 10 Pin Name Listing Pin Name Pin Signal Buffer Type Direction VSS AA2 Power Other VSS AA5 Power Other VSS...

Page 48: ...wer Other VSS AE16 Power Other VSS AE19 Power Other VSS AE23 Power Other Table 10 Pin Name Listing Pin Name Pin Signal Buffer Type Direction VSS AE26 Power Other VSS AF2 Power Other VSS AF6 Power Othe...

Page 49: ...Other VSS E16 Power Other VSS E19 Power Other VSS E21 Power Other Table 10 Pin Name Listing Pin Name Pin Signal Buffer Type Direction VSS E24 Power Other VSS F2 Power Other VSS F5 Power Other VSS F8...

Page 50: ...Other VSS P21 Power Other VSS P24 Power Other VSS R2 Power Other VSS R5 Power Other Table 10 Pin Name Listing Pin Name Pin Signal Buffer Type Direction VSS R22 Power Other VSS R25 Power Other VSS T1...

Page 51: ...C Power Other A11 VSS Power Other A12 VCC Power Other A13 VCC Power Other A14 VSS Power Other A15 VCC Power Other A16 VSS Power Other A17 VCC Power Other A18 VCC Power Other A19 VSS Power Other A20 VC...

Page 52: ...er AB20 VCC Power Other AB21 D 52 Source Synch Input Output Table 11 Pin Listing Pin Pin Name Signal Buffer Type Direction AB22 D 51 Source Synch Input Output AB23 VSS Power Other AB24 D 33 Source Syn...

Page 53: ...VSS Power Other AE9 VCC Power Other AE10 VCC Power Other AE11 VSS Power Other AE12 VCC Power Other Table 11 Pin Listing Pin Pin Name Signal Buffer Type Direction AE13 VCC Power Other AE14 VSS Power O...

Page 54: ...GNNE CMOS Input C5 VSS Power Other C6 LINT0 CMOS Input C7 THERMTRI P Open Drain Output Table 11 Pin Listing Pin Pin Name Signal Buffer Type Direction C8 VSS Power Other C9 VCC Power Other C10 VCC Powe...

Page 55: ...Synch Input Output F1 BR0 Common Clock Input Output Table 11 Pin Listing Pin Pin Name Signal Buffer Type Direction F2 VSS Power Other F3 RS 0 Common Clock Input F4 RS 1 Common Clock Input F5 VSS Powe...

Page 56: ...Input Output K1 VSS Power Other K2 REQ 2 Source Synch Input Output Table 11 Pin Listing Pin Pin Name Signal Buffer Type Direction K3 REQ 0 Source Synch Input Output K4 VSS Power Other K5 A 6 Source S...

Page 57: ...Output P24 VSS Power Other P25 D 24 Source Synch Input Output Table 11 Pin Listing Pin Pin Name Signal Buffer Type Direction P26 D 18 Source Synch Input Output R1 A 16 Source Synch Input Output R2 VS...

Page 58: ...SS Power Other W2 A 27 Source Synch Input Output W3 A 32 Source Synch Input Output W4 VSS Power Other W5 A 28 Source Synch Input Output W6 A 20 Source Synch Input Output W21 VCCP Power Other W22 D 41...

Page 59: ...ion ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 and REQ 4 0 pins All bus agents observe the ADS activation to begin parity checkin...

Page 60: ...ust connect the appropriate pins on both agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock perio...

Page 61: ...PRSTP must be deasserted DPRSTP is driven by the ICH9M DPSLP Input DPSLP when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state To return to the...

Page 62: ...GTLREF should be set at 2 3 VCCP GTLREF is used by the AGTL receivers to determine if a signal is a logical 0 or logical 1 HIT HITM Input Output Input Output HIT Snoop Hit and HITM Hit Modified conve...

Page 63: ...onfiguration LOCK Input Output LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of both FSB agents For a locked sequence of transacti...

Page 64: ...die pull up resistor on this signal RS 2 0 Input RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropria...

Page 65: ...Input Refer to the appropriate platform design guide for further TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 and TEST7 termination requirements and implementation details THRMDA Other Thermal Diode Anode THRM...

Page 66: ...processor The voltage supply for these pins must be valid before the VR can supply VCC to the processor Conversely the VR output must be disabled until the voltage supply for the VID pins becomes val...

Page 67: ...nd long term reliability of Intel processor based systems the system processor thermal solution should be designed so the processor remains within the minimum and maximum junction temperature TJ speci...

Page 68: ...ndicate that the maximum TJ has been reached 4 The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications 5 At Tj of 105 o C 6 At Tj of 50 o C 7 At Tj...

Page 69: ...t is connected to the transistor The processor however is built on Intel s advanced 45 nm processor technology Due to this new processor technology it is no longer possible to model the substrate tran...

Page 70: ...ambient environment may cause a noticeable performance loss and may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be cap...

Page 71: ...within the processor If both TM1 and TM2 bits are enabled in the auto throttle MSR TM2 takes precedence over TM1 However if Force TM1 over TM2 is enabled in MSRs via BIOS and TM2 is not sufficient to...

Page 72: ...tion 5 1 3 Digital Thermal Sensor The processor also contains an on die Digital Thermal Sensor DTS that can be read via an MSR no I O interface Each core of the processor will have a unique digital th...

Page 73: ...e PROCHOT pin exists at a package level of the processor When either core s thermal sensor trips PROCHOT signal will be driven by the processor package If only TM1 is enabled PROCHOT will be asserted...

Page 74: ...s 74 Datasheet of time when running the most power intensive applications An under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient envir...

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