82540EP — Networking Silicon
2
Datasheet
Figure 1. Gigabit Ethernet Controller Block Diagram
Tx
Ar
b
PC
I
i/
f
PC
I I
/F
RX M
A
C
TX
M
A
C
TX
d
e
scri
p
to
r
e
ngi
n
e
Data Alignment
FI
F
O
s
PC
I
Co
re
DM
A
MA
C
C
o
re
82
54
0E
P
Ar
ch
it
ec
tu
re
P
acke
t B
u
ff
e
r
Ta
rg
et
C
ont
ro
l
C
o
nt
ro
l,
S
tat
us
& In
te
rru
p
t
Re
g
is
te
rs
Ta
rg
et
Lo
gi
c
Fi
lte
r
St
a
tis
tic
s
Packet Buffer Interface
AC
P
I
TX
RX
RX
In
TX
Ou
t
HW
D
e
faul
t
C
onfi
g
s
RX
Da
ta
TX
Lin
k
MD
I
(C
oppe
r)
In
te
rfa
ce
4
-wire
E
E
P
R
OM
In
te
rfa
ce
MD
IO
Fl
as
h
F
la
sh
In
te
rfa
ce
Cl
o
c
k
/
Re
s
e
t
EE
PRO
M
Ma
st
e
r
re
a
d
FI
FO
Ma
st
e
r
wri
te
FIF
O
RX
de
s
c
ript
o
r
en
gi
ne
FI
FOs
(M
a
n
y
bl
oc
k
s
)
64K
b
y
te
s
LE
D
ASF
PHY
S
M
B
u
s I
n
te
rf
ace
TX Data
RX Da
ta
CS
R Re
g
is
te
r
A
ccess
CSR Register
Access
Mg
mt
FIF
O
s
Ma
n
a
g
e
a
b
il
it
y
Fl
ow
Ctr
l
GM
II
