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Intel 82540EP, Datasheet

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Intel 82540EP Datasheet Download Page 34

82540EP — Networking Silicon

28

Datasheet

 

5.2

Package Information

The 82540EP device is a 196-lead ball grid array (TFBGA) measuring 15 mm

2

. The package 

dimensions are detailed in 

Figure 11

. The nominal ball pitch is 1 mm. 

Figure 11. 82540EP Mechanical Specifications

Summary of Contents for 82540EP

Page 1: ...82540EP Gigabit Ethernet Controller Networking Silicon Datasheet Revision 1 2 April 2003...

Page 2: ...time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no...

Page 3: ...tial Jan 2003 1 1 Section 1 0 Replaced Block Diagram Section 2 6 Added Table footnote Section 4 1 4 2 4 3 Replaced tables Section 5 1 Added Visual Pin Reference Section 4 4 Removed Power Supply Charac...

Page 4: ...82540EP Networking Silicon iv Datasheet Note This page is intentionally left blank...

Page 5: ...System Signals 11 3 2 5 Error Reporting Signals 11 3 2 6 Power Management Signals 12 3 2 7 Impedance Compensation Signals 12 3 2 8 SMB Signals 12 3 3 EEPROM and Serial FLASH Interface Signals 12 3 4...

Page 6: ...icon vi Datasheet 4 5 3 EEPROM Interface 26 5 0 Package and Pinout Information 27 5 1 Device Identification 27 5 2 Package Information 28 5 3 Thermal Specifications 29 5 4 Pinout Information 30 5 5 Vi...

Page 7: ...eability implementations required by information technology personnel for remote control and alerting via the LAN With SMB management packets can be routed to or from a management processor The SMB po...

Page 8: ...trol Status Interrupt Registers Target Logic Filter Statistics Packet Buffer Interface ACPI TX RX RX In TX Out HW Default Configs RX Data TX Link MDI Copper Interface 4 wire EEPROM Interface MDIO Flas...

Page 9: ...CI Special Interest Group PCI Bus Power Management Interface Specification Rev 1 1 PCI Special Interest Group IEEE Standard 802 3 1996 Edition Institute of Electrical and Electronics Engineers IEEE IE...

Page 10: ...82540EP Networking Silicon 4 Datasheet Note This page is intentionally left blank...

Page 11: ...port with software controllable pause times and threshold values Control over the transmissions of pause frames through software or hardware triggering Frame loss reduced from receive overruns Caches...

Page 12: ...d maintenance End to end wiring tolerance Features Benefits Transmit and receive IP TCP and UDP checksum off loading capabilities Lower CPU utilization Transmit TCP segmentation Increased throughput a...

Page 13: ...mpliant including D0 and D3 power states Network Device Class Power Management Specification 1 1 PCI Specification 2 2 PCI power management capability requirements for PC and embedded applications SNM...

Page 14: ...ed I O devices Supports little endian byte ordering for both 32 and 64 bit systems and big endian byte ordering for 64 bit systems Portable across application architectures Two or three pair cable dow...

Page 15: ...ting it float The next agent of the signal cannot drive the pin earlier than one clock after it has been released by the previous agent OD Open Drain Wired OR with other agents The signaling agent ass...

Page 16: ...ndicates the master is ready to accept data Wait cycles are inserted until both IRDY and TRDY are asserted together The 82540EP controller drives IRDY when acting as a master and samples it when actin...

Page 17: ...eters are defined with respect to this edge M66EN I 66 MHz Enable M66EN indicates whether the system bus is enabled for 66MHz RST I PCI Reset When the PCI Reset signal is asserted all PCI output signa...

Page 18: ...is indicative of the PCI trace load This cell is used to dynamically determine the drive strength required on the N channel transistors in the PCI I O cells ZP_COMP I O P Device Impedance Compensatio...

Page 19: ...to indicate link connectivity LED1 ACT O LED1 Activity Programmable LED indication Defaults to flash to indicate transmit or receive activity LED2 LINK100 O LED2 LINK 100 Programmable LED indication D...

Page 20: ...configuration MDI 0 is used for the transmit pair and in MDI X configuration MDI 0 is used for the receive pair 10BASE T In MDI configuration MDI 0 is used for the transmit pair and in MDI X configur...

Page 21: ...active low reset signal for JTAG This signal should be terminated using a pull down resistor to ground It must not be left unconnected TEST I Factory Test Pin CLKVIEW O Clock View Output for GTX_CLK a...

Page 22: ...egulator output to drive external pass transistor If 1 5V is already present in the system leave output unconnected To achieve optimal D3 power consumption 50 mw leave the output unconnected and use a...

Page 23: ...ngsa Symbol Parameter Min Max Unit VDD DC supply voltage 0 3 7 V VIN Input voltage 1 VDD 0 3 V IIN DC input pin current 10 10 mA TSTG Storage temperature 40 125 C a Maximum ratings are referenced to g...

Page 24: ...Symbol Parameter Min Typ Max Units VDD 3 3 DC supply voltage on VDDO or AVDDH 3 00 3 3 3 60 V VDD 2 5 DC supply voltage on AVDDL 2 38 2 5 2 62 V VDD 1 5 DC supply voltage on DVDD 1 43 1 5 1 57 V Table...

Page 25: ...mode do not use the internal voltage regulator control circuit and external pass transis tors Use external switching regulators for highest efficiency Table 6 Power Specifications D r Uninitialized D...

Page 26: ...ers TTL12 VOL VOL VOL 3 6 12 mA mA mA IOH a Output current HIGH 3mA drivers TTL3 6mA drivers TTL6 12mA drivers TTL12 VOH VOH VOH 3 6 12 mA mA mA IIN Input Current TTL inputs Inputs with pull down resi...

Page 27: ...to the Crystal One XTAL1 input Alternatively a crystal may be connected to XTAL1 and XTAL2 as the frequency source for the internal oscillator Table 11 Link Interface Clock Requirements Symbol Parame...

Page 28: ...ms of the edge rate measured in V ns This slew rate must be met across the minimum peak to peak portion of the clock waveform as shown PCI 66 MHz PCI 33 MHz Units Min Max Min Max TCYC CLK cycle time 1...

Page 29: ...I 33 MHz Units Min Max Min Max TVAL CLK to signal valid delay bussed signals 2 6 2 11 ns TVAL ptp CLK to signal valid delay point to point signals 2 6 2 12 ns TON Float to active delay 2 2 ns TOFF Act...

Page 30: ...ut Valid TH Table 16 PCI Bus Interface Timing Measurement Conditions Symbol Parameter PCI 66 MHz 3 3 v Unit VTH Input measurement test voltage high 0 6 VCC V VTL Input measurement test voltage low 0 2...

Page 31: ...Minimum times are specified with 0 pF load Figure 6 TVAL max Falling Edge Test Load 10 pF 25 Pin Test Point 1 2 inch max VCC Figure 7 TVAL min Test Load 1k Pin Test Point 1 2 inch max VCC 10 pF 1k Fig...

Page 32: ...7 ns TR Data rise time 0 8 to 2 0 V 0 7 ns TF Data fall time 2 0 V to 0 8 V 0 7 ns Figure 9 Link Interface Rise Fall Timing Table 18 Link Interface Clock Requirements Symbol Parameter Min Typ Max Unit...

Page 33: ...in Figure 10 The nominal ball pitch is 1mm The pin number to signal mapping is indicated beginning with Table 19 5 1 Device Identification NOTE indicates the location of pin 1 It is not an actual mark...

Page 34: ...Datasheet 5 2 Package Information The 82540EP device is a 196 lead ball grid array TFBGA measuring 15 mm2 The package dimensions are detailed in Figure 11 The nominal ball pitch is 1 mm Figure 11 8254...

Page 35: ...ermal resistances are shown in Table 18 Thermal resistances are determined empirically with test devices mounted on standard thermal test boards Real system designs may have different characteristics...

Page 36: ...4 PCI_AD 22 B1 IRDY F1 PCI_AD 7 N4 PCI_AD 23 B2 TRDY G3 PCI_AD 8 P3 PCI_AD 24 B4 STOP H1 PCI_AD 9 N3 PCI_AD 25 A5 DEVSEL H3 PCI_AD 10 N2 PCI_AD 26 B5 VIO G2 PCI_AD 11 M1 PCI_AD 27 B6 IDSEL A4 PCI_AD 1...

Page 37: ...nal Pin SMBCLK A10 SMBDATA C9 SMBALRT B10 Table 27 EEPROM and Serial FLASH Interface Signals Signal Pin Signal Pin Signal Pin EE_SK M10 EE_DI P10 FL_SCK N9 EE_DO N10 FL_CE M9 FLSO P9 EE_CS P7 FL_SI M1...

Page 38: ...J8 DVDD 1 5V L9 DVDD 1 5V E12 DVDD 1 5V J9 DVDD 1 5V L10 DVDD 1 5V G5 DVDD 1 5V J10 VDDO 3 3V A3 DVDD 1 5V G6 DVDD 1 5V J11 VDDO 3 3V A7 DVDD 1 5V G13 DVDD 1 5V K5 VDDO 3 3V A11 DVDD 1 5V H5 DVDD 1 5...

Page 39: ...D14 GND D6 GND F6 GND K2 NC F12 GND D7 GND F7 GND K12 NC H12 GND D8 GND F8 GND L6 NC J4 GND D13 GND F9 GND L11 NC J13 GND E2 GND F10 GND M6 NC L7 GND E4 GND F11 GND N1 NC N11 GND E5 GND G7 GND N12 NC...

Page 40: ...REF B14 PCI_AD 21 C1 M66EN C2 REQ C3 CBE3 C4 NC C5 PCI_AD 28 C6 PCI_AD 29 C7 CLKRUN C8 SMBDATA C9 GND C10 LED1 ACT C11 GND C12 MDI0 C13 MDI0 C14 PCI_AD 18 D1 PCI_AD 19 D2 PCI_AD 20 D3 GND D4 GND D5 GN...

Page 41: ...E10 DVDD 1 5V E11 DVDD 1 5V E12 MDI1 E13 MDI1 E14 IRDY F1 FRAME F2 CBE2 F3 GND F4 GND F5 GND F6 GND F7 GND F8 GND F9 GND F10 GND F11 NC F12 MDI2 F13 MDI2 F14 CLK G1 VIO G2 TRDY G3 ZP_COMP G4 DVDD 1 5V...

Page 42: ...DVDD 1 5V H8 GND H9 GND H10 DVDD 1 5V H11 NC H12 MDI3 H13 MDI3 H14 PAR J1 PERR J2 GNT J3 NC J4 DVDD 1 5V J5 DVDD 1 5V J6 DVDD 1 5V J7 DVDD 1 5V J8 DVDD 1 5V J9 DVDD 1 5V J10 DVDD 1 5V J11 AUX_PWR J12...

Page 43: ...VDD 1 5V L4 DVDD 1 5V L5 GND L6 NC L7 AVDDL 2 5 V L8 DVDD 1 5V L9 DVDD 1 5V L10 GND L11 JTAG_TMS L12 JTAG_RST L13 JTAG_TCK L14 PCI_AD 11 M1 PCI_AD 12 M2 PCI_AD 13 M3 CBE0 M4 PCI_AD 5 M5 GND M6 PCI_AD...

Page 44: ..._AD 0 N7 VDDO 3 3V N8 FL_SCK N9 EE_DO N10 NC N11 GND N12 SDP6 N13 SDP0 N14 NC P1 VDDO 3 3V P2 PCI_AD 8 P3 PCI_AD 6 P4 PCI_AD 3 P5 PCI_AD 2 P6 EE_CS P7 GND P8 FL_SO P9 EE_DI P10 CTRL_15 P11 VDDO 3 3V P...

Page 45: ...S VSS VSS 1 5V 1 5V 1 5V EESK EEDO EEDI 10 9 LAN PWRGD RST SMB DAT 2 5V PHY VSS VSS VSS VSS 1 5V 1 5V 1 5V FLSH CE_N FLSH SCK FLSH SO 9 8 AD30 AD31 CLK RUN VSS VSS VSS VSS 1 5V 1 5V 1 5V 2 5V PHY CLK...

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