Intel
®
81341 and 81342 I/O Processors
December 2007
Developer’s Manual
Order Number: 315037-002US
571
DDR SDRAM Memory Controller—Intel
®
81341 and 81342
7.3.2.3
North Internal Bus Port Preemption
In order to maximize core processor performance, the DMARB can be programmed to
interrupt active transactions from other memory ports, in order to process transactions
from the north internal bus (Core Processors). By preempting an active transaction, the
DMARB ensures a maximum number of data cycles getting processed for the current
transaction, therefore reducing the possible latency the Core Processor might see for
memory accesses. Core processor preemption is enabled through the DMARB
Preemption Control Register (DMPCR).
Preemption control applies to all inbound DMCU ports based on pending north internal
bus transactions. Once the north internal bus transaction queue is ‘activated’ by the
DMARB, a standard tenure takes place. At the completion of the north internal bus
transaction queue tenure, the DMARB resumes the previously active transaction. The
previously active transaction may be interrupted again, provided the conditions for
preemption occur again prior to the completion of that transaction. No other effect on
the DMARB processing occurs.
7.3.2.4
North Internal Bus Port Transaction Ordering
The North IB port maintains order of requests (core requests) addressing the DDR
SDRAM. Coherency between the north IB port, south IB port and the other ports are
maintained by the DMCU as described in
below.
7.3.2.5
South Internal Bus Port Ordering
The IB port implements ordering of like transactions where reads do not pass reads,
and writes do not pass writes. Write transactions are allowed to pass read transactions.
Read transactions are processed by the DMCU as described in
below.
7.3.2.6
Application DMAs Port Ordering
The Application DMA port implements ordering of like transactions where reads do not
pass reads, and writes do not pass writes. Write transactions are allowed to pass read
transactions. Read transactions are processed by the DMCU as described in
below.
7.3.2.7
DMCU Port Coherency
With the queueing of DDR SDRAM transactions in multiple ports, coherency of memory
must be maintained. The DMARB maintains memory coherency by ensuring that all
writes to a given memory address are completed before any read to the same address
is processed. This address comparison is done with a 1 KByte granularity.
The highest priority Read transaction is compared to all pending write transactions from
all memory transaction queues (north IB and south IB port queues). When a write
transaction is pending for the same memory location (1 KByte granularity), the write is
allowed to complete first, before the read transaction is processed. Also, to maintain
ordering rules, all write transactions preceding the ‘incoherent write’ are also
processed.
