Intel 80331, Design Manual

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Intel® 80331 I/O Processor Design Guide
Memory Controller
7.5.3.2 DDRII 400 Clock Routing Guidelines
This section lists the recommendations for the DDR II 400 Clock signals. Refer to Figure 52 and
Table 61 for a description of the segment lengths and matching requirements.
Table 61. DDRII 400 DIMM Clock Routing Recommendations
Parameter Routing Guideline
Reference Plane Unbroken Ground plane
Preferred Topology
Microstrip differential lines (preferred)
Stripline differential lines
Microstrip Trace Width and spacing 5 mils by 5 mils.
Trace Impedance
Differential impedance of 100 ohms +/- 15%
Refer to DIMM Clock Topology
Trace Spacing > 20 mils between other signals.
Trace Length 1:80331signal Ball to DIMM connector
2.0”min to 10.0” max correlated within the +/- 1.0” of
the DQ/DQS and command signal length (from 80331
to DIMM connector).
Length Matching:
• Within differential clock signals
• With respect to DQ/DQS group (from controller to
DIMM connector)
• With respect to address/command group (from
controller to DIMM connector)
+/- 0.0250” within pairs (intra-pair)
+/- 1.0” maximum
+/- 1.0” maximum
Routing Guideline 1
Maximum of 1 via/layer change for differential clocks.
(use the same number of vias b and - signals
of differential clock)
Routing Guideline 2
Route clock signal as differential pair with target
differential impedance of 100 ohms.
Table 62. DDR II 400 DIMM Clock Lengths
Traces Description Layer
Minimum
Length
Maximum
Length
Trace
Impedance
Spacing
(edge to
edge)
Notes
TL0 Breakout
Microstrip or
stripline
0” 0.5” 5 mils
5 mils trace width OK for
breakout.
TL1 Lead-in
Microstrip or
stripline
2 “ 10”
Differential
Impedance of
100 ohms Other
groups
20 mils
Route as differential pair with
target impedance of 100 ohms
correlated within the +/- 1.0” of
the DQ/DQS and command
signal length (from 80331 to
DIMM connector).
Figure 52. DDR II 400 DIMM Clock Topology
TL0 TL1