Integra DTR-5.9, Service Manual, Page: 74 / 212

DTR-5.9
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-37
Q8401 : SiI9134CTU (HDMI Deep Color Transmitter)-3/4
TERMINAL DESCRIPTION
Pin Name
D0 - D11
D12 - D23
D24 - D35
Pin #
98 - 84
83 - 71
70 - 56
Dir
Input
Input
Input
Description
These are the lower 12 bits of the 36-bit pixel bus.
These pins are highly configurable, and support multiple RGB and YCbCr formats.
These are the middle 12 bits of the 36-bit pixel bus.
These are the upper 12 bits of the 36-bit pixel bus.
Video and Audio Input pins
Pin Name
HPD
RSVDL
INT
Pin #
51
52
24
Dir
Input
Input
Output
Description
Hot Plug Detect Input.
Reserved for use by Silicon Image and must be tied LOW.
Interrupt Output.
Video and Audio Input pins
Control Pins
Pin Name
CI2CA
RESET#
CSCL
CSDA
DSCL
DSDA
Pin #
50
25
48
49
46
47
Dir
Input
Input
Input
Bi-Di
Bi-Di
Bi-Di
Description
I C device address select
Reset Pin (Active LOW) 5V Tolerant
I C Clock
I C Data (Open Drain Output)
DDC Clock (Open Drain Output)
DDC Data (Open Drain Output)
2
2
2
Pin Name
IDCK
DE
HSYNC
VSYNC
SCK
WS
SD0
SD1
SD2
SD3
DL0
DR0
DL1
DR1
DL2
DR2
DL3
DR3
DCLK
MCLK
SPDIF
Pin #
88
1
2
3
11
10
9
8
7
6
17
16
19
18
21
20
23
22
15
5
4
Dir
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
Input Data clock
Data enable
Horizontal Sync input control signal
Vertical Sync input control signal
I S Serial Clock
I S Word Select
I S Serial data
I S Serial data
I S Serial data
I S Serial data
One-bit Audio data Left 0
One-bit Audio data Right 0
One-bit Audio data Left 1
One-bit Audio data Right 1
One-bit Audio data Left 2
One-bit Audio data Right 2
One-bit Audio data Left 3
One-bit Audio data Right 3
One-bit Audio Clock Input
Audio Input Master Clock
S/PDIF Audio Input.
Configuration / Programming Pins
2
2
2
2
2
2