DTR-5.9
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-2
Q201
: D788E001BRFP266 (Floating-Point Digital Signal Processor)-2/5
PIN LAYOUT
144-pin RFP
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
VSS
EM_CKE
EM_CLK
VSS
DVDD
EM_WE_DQM[1]
EM_D[8]
CVDD
EM_D[9]
EM_D[10]
VSS
EM_D[11]
DVDD
EM_D[12]
EM_D[13]
CVDD
EM_D[14]
EM_D[15]
VSS
CVDD
EM_D[0]
EM_D[1]
DVDD
EM_D[2]
EM_D[3]
VSS
EM_D[4]
EM_D[5]
CVDD
EM_D[6]
DVDD
EM_D[7]
VSS
EM_WE_DQM[0]
EM_WE
EM_CAS
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
SPI0_CLK/I2C0_SCL
SPI0_SCS/I2C1_SCL
VSS
SPI0_ENA/I2C1_SDA
EM_OE
DVDD
EM_RW
CVDD
EM_CS[2]
VSS
EM_RAS
EM_CS[0]
EM_BA[0]
VSS
EM_BA[1]
EM_A[10]
DVDD
EM_A[0]
CVDD
EM_A[1]
EM_A[2]
VSS
EM_A[3]
CVDD
EM_A[4]
EM_A[5]
VSS
DVDD
EM_A[6]
EM_A[7]
VSS
CVDD
EM_A[8]
EM_A[9]
EM_A[11]
DVDD
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VSS
SPI0_SIMO
SPI0_SOMI/I2C0_SDA
DVDD
AXR0[0]
VSS
AXR0[1]
AXR0[2]
AXR0[3]
VSS
AXR0[4]
AXR0[5]/SPI1_SCS
AXR0[6]/SPI1_ENA
AXR0[7]/SPI1_CLK
CVDD
VSS
DVDD
AXR0[8]/AXR1[5]/SPI1_SOMI
AXR0[9]/AXR1[4]/SPI1_SIMO
CVDD
VSS
AXR0[10]/AXR1[3]
AXR0[11]/AXR1[2]
CVDD
VSS
AXR0[12]/AXR1[1]
AXR0[13]/AXR1[0]
DVDD
AXR0[14]/AXR2[1]
AXR0[15]/AXR2[0]
ACLKR0
VSS
AFSR0
ACLKX0
AHCLKR0/AHCLKR1
AFSX0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VSS
AHCLKX0/AHCLKX2
AMUTE0
AMUTE1
AHCLKX1
VSS
ACLKX1
CVDD
ACLKR1
DVDD
AFSX1
AFSR1
VSS
RESET
VSS
CVDD
CLKIN
VSS
TMS
CVDD
TRST
OSCVSS
OSCIN
OSCOUT
OSCVDD
VSS
PLLHV
TDI
TDO
VSS
DVDD
EMU[0]
CVDD
EMU[1]
TCK
VSS