User Manual | PE11S100X Series Synthesizer
22
7.5 Reg 03h Reserved
Bit
Type
Name
Default
Description
13:0
R/W
rfp_div_ratio, also
referred to as “R”
1
16:14
R/W
Reserved
7
Reserved
7.6 Reg 04h Prescaler Duty Cycle Register
Bit
Type
Name
Default
Description
0
R/W
vcop_dutycycmode
1
Extends the low time from 15 to 47 VCO cycles
for large divide ratios
7.7 Reg 05h Reserved
Bit
Type
Name
Default
Description
2:0
R/W
Reserved
7
Reserved
7.8 Reg 06h Phase Freq Detector Delay Register
Bit
Type
Name
Default
Description
2:0
R/W
pfd_del_sel
2
Delay line setpoint to PFD
7.9 Reg 07h Charge Pump UP/DN Control Register
Bit
Type
Name
Default
Description
4:0
R/W
cp_UPcurrent_sel
16
Sets Charge-
Pump Up gain, 125 μA lsb, binary,
4 mA max
9:5
R/W
cp_DNcurrent_sel
16
Sets Charge-
Pump Dn gain, 125 μA lsb, binary,
4 mA max
7.10 Reg 08h Charge Pump Trim & Offset Register
Bit
Type
Name
Default
Description
3:0
R/W
cp_UPtrim_sel
0
Trim Up gain, 14.3μA lsb, binary, 100μA max
7:4
R/W
cp_DNtrim_sel
0
Trim Dn gain, 14.3μA lsb, binary, 100μA max
