User Manual | PE11S100X Series Synthesizer
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DC leakage or “offset” may be added to the UP or DN pumps using cp_UPoffset_sel and cp_DNoffset_sel
(
). These are 4 bit registers with 28.7 μA LSB. Maximum offset is 430 μA.
As an example, if the main pump gain was set at 1 mA, an offset of 373 μ
A would represent a phase offset
of about (392/1000)*360 = 133 degrees
4.5.4 Charge Pump Operation Near the Minimum & Maximum Output Frequency
It should be noted that the charge pump is a non-ideal device. Operation of the module tuned to values
near the minimum or maximum output frequency results in degradation of the phase noise performance.
When operating near the minimum or maximum frequencies, it is recommended to operate the PE11S100X
synthesizer modules with a DC leakage that mirrors the direction of frequency offset from center frequency.
For example, if the PE11S100X synthesizer modules operates from 5 to 10 GHz, with a center frequency
of 7.5 GHz, and the desired frequency of operation is 5.5 GHz, it is recommended to operate with a DC
leakage in the down direction. The converse is also true. If operating the module near its maximum
frequency, then a DC leakage in the UP direction is recommended. The appropriate leakage value is
application dependent and it is left to the user to determine the appropriate setting based on the application
requirements.
4.6 Power On Reset (POR)
Normally all logic cells in the internal PLL are reset when the device digital power supply, Vd1,
is applied. This is referred to as Power On Reset, or just POR. POR normally takes about 500
us after the Vd1 supply exceeds 1.6 V, guaranteed to be reset in 1 ms. Once the Vd1 supply
exceeds 1.6 V, the POR will not reset the digital again unless the supply drops below 800 mV.
4.6.1 Soft Reset
The SPI registers may also be soft reset by an SPI write to strobe global_swrst_regs (
<0>).
All other digital items, including the fractional modulator, may be reset with an SPI write to strobe global_
swrst_dig (
<1>).
4.6.2 Power Down
The internal PLL chip may be powered down by writing a zero to
. In power down state, VD1 will
draw less than 1 mA. Note that a signal will still be present at the output (frequency may be anywhere in
the VCO tune range). It should be noted that
is the Enable and Reset Register which controls 16
separate functions in the chip. Depending upon the desired mode of operation of the chip, not all of the
functions may be enabled when in operation. Hence power up of the chip requires a selective write to
bits. An easy way to return the chip to its prior state after a power down is to first read
and
save the state, then write a zero to
for reset and then simply rewrite the previous value to restore
the chip to the desired operating mode.
5.0 Serial Port
The serial port is designed to operate on 3.3 V logic signals. At no time should levels above 3.6 V be applied
to these pins.
Typical serial port operation can be run with SCK at speeds up to 50 MHz.
