User Manual
290
Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
Memory Control Unit
Figure 46 Memory Control Unit Block View
Functional Features for RAM
• 4 KB (product variant dependant) RAM
• Error correction code (ECC) for detection of single bit and double bit errors and dynamic correction of
single bit errors
• Single byte access
As shown in the
, the Memory Control Unit interface communicates with the external world, mainly
the core, via 4 AHB-Lite interfaces, Data/Code access to the NVM, BootROM and RAM plus an access to the NVM
internal registers. The AMBA bus matrix block decodes the access requests coming from the masters and
forwards them to the target module interface together with the required sideband signals. The AMBA bus
matrix block provides all the needed interface functions between the masters and the memory peripheral. It
will generate proper HSEL signals, and multiplex the response coming from the modules. In addition, the
AMBA bus matrix block takes care of forwarding the transfer according the a fixed priority policy described in
the AMBA chapter.
Besides the AHB-Lite and sideband signals, the Memory Control Unit has access to further Core specific
signals, relevant for memory protection .
MCU_Block_Diagram_overview.vsd
Bus Matrix
RAM
ROM
S0
Memory Protection
Unit
S1
S2
NV
M
Co
de
/ Da
ta
M1
M2
RA
M
Co
de
/ D
ata
RO
M
Co
de
/ D
ata
M0
PBA0
S3
M3
Sx: Bus Slave
Mx: Bus Master
NVM
