By convention, files targeted to run on the CM0+ CPU are located in the
CM0p
folder and files targeted to run on
the CM4 CPU are located in the
CM4
folder.
Figure 25
Setting target processor for a source C file
4.6
Part 4: Write the firmware
At this point in the development process, you have created a project, implemented a hardware design, and
generated the code. In this part, you write the firmware that implements the design functionality.
The steps in this part discuss the firmware for the design that you configured in
The code example has all the required code. If you are working from scratch, you can copy the respective source
codes to
main_cm0p.c
and
main_cm4.c
from the code snippet provided in this section. If you are using the code
example, files are already in your project.
Firmware flow
In the remaining steps, we examine code in the
main_cm0p.c
and
main_cm4.c
file.
When the PSoC
™
6 MCU device is reset, the firmware first performs system initialization, which includes setting
up the CPUs for execution, enabling global interrupts, and enabling other Components used in the design.
The initialization is split across the CPUs. The CM0+ CPU comes out of reset and enables the CM4 CPU. The
CM0+ CPU code snippet is given in
. Copy the following code snippet to the
main_cm0p.c
file of your
project.
Getting started with PSoC
™
6 MCU on PSoC
™
Creator
4 My first PSoC
™
6 MCU design using PSoC
™
Creator
Application Note
29
002-21774 Rev. *G
2022-07-21
