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Additional Information 

7 of 20 

Revision 6.0  

 

 

2020-11-12 

 

Recommendations for Board Assembly of Infineon Quad Flat 
Packages 

  

Printed Circuit Board 

   

2

 

Printed Circuit Board 

2.1

 

Routing 

Printed circuit board design and construction are key factors for achieving solder joints with high reliability. 
Packages with exposed pads should not be placed opposite to each other on either side of a PCB when doing 
double-sided mounting. This will stiffen the assembly and cause solder joints to fatigue earlier than in a design 
in which the components are offset. Furthermore, the board stiffness itself has a significant influence on the 
reliability of the solder joint interconnect if the system is used in critical temperature-cycling conditions. 

2.2

 

Pad Design 

The quality and reliability of interconnect solder joints to the board are affected by: 

 

Pad type (Solder-Mask Defined, SMD or Non-Solder-Mask Defined, NSMD) 

 

Specific pad dimensions 

 

Pad finish (also called metallization or final finish) 

 

Via layout and technology 

The NSMD pad design is recommended for QFP components. The approach applies to the peripheral 
terminations as well as to the exposed pads. Mixing different pad definition types in one footprint is not 
recommended. 

The exposed pads of QFP can feature anti-flash profiles. These are meander structures at the outline of the pad 
to taper off potential mold flash during fabrication process. In 

Figure 4

 such an anti-flash profile is shown. 

Despite that structure, the exposed pad outline is used for soldering purpose as can be seen in 

Figure 5

. 

Besides their electrical function, the exposed pad areas of QFP packages are designed to conduct high thermal 
loads into the PCB in order to achieve an optimal thermal performance. Therefore, the exposed pad area on the 
PCB should be congruent with the area on the package at minimum. Using a PCB pad of the same size as the 
package exposed pad will also increase the solder joint reliability, and the electrical performance for some 
applications

Figure 5

 shows an example of print pattern on a PCB pad for a die pad connection including 

thermal vias. 

 

 

Figure 4

 

QFP with anti-flash profile in the exposed pad. The outer extension of the exposed pad 
including the anti-flash profile should be used as the reference for the PCB pad design. 

 

Summary of Contents for PG-LQFP

Page 1: ...al Information Please read the Important Notice and Warnings at the end of this document Revision 6 0 www infineon com page 1 of 20 2020 11 12 Recommendations for Board Assembly of Infineon Quad Flat...

Page 2: ...1 1 QFP Package Type 4 1 2 Package Features and General Handling Guidelines 4 2 Printed Circuit Board 7 2 1 Routing 7 2 2 Pad Design 7 2 3 Via in Pad Design 9 3 PCB Assembly 11 3 1 Solder Paste Stenci...

Page 3: ...ge IC Integrated Circuit I O Input Output LF Lead Frame LQFP Low profile Quad Flat Package MQFP Metric Quad Flat Packages MSL Moisture Sensitivity Level Ni Pd Au Nickel Palladium Gold NSMD Non Solder...

Page 4: ...ches The typical pitch of Low profile Quad Flat Packages LQFP and Thin Quad Flat Packages TQFP is of 0 5 mm The latter also provides a pitch down to 0 4 mm Metric Quad Flat Packages MQFP have a typica...

Page 5: ...hen soldered to the PCB The distance between the I O lead seating plane and the exposed pad landing area at the package bottom is defined as the package stand off On QFP it can vary around the nominal...

Page 6: ...of Infineon Quad Flat Packages Package Description Figure 3 Soldered gullwing leads with post mold plated Sn left and with pre plated Ni Pd Au right For further information about the specific compone...

Page 7: ...ed for QFP components The approach applies to the peripheral terminations as well as to the exposed pads Mixing different pad definition types in one footprint is not recommended The exposed pads of Q...

Page 8: ...to the lead top plane is used to take into account the lower bend angle The PCB pad and therefore the solder paste print should have a distinct distance to the package mold in order to avoid an uncle...

Page 9: ...One of the primary exposed pad design objectives besides the thermal management should be to avoid the penetration of the vias by solder Consequences of solder penetration can be a decreased stand of...

Page 10: ...g voids during reflow soldering In case it is not necessary to provide a direct connection from the solder pad under the exposed die pad to the inner layers of the PCB the vias can be placed next to t...

Page 11: ...l design adaptations to reach the optimum amount of solder the stencil thickness the PCB pad finish solder mask quality the via layout and the solder paste type should be considered In every case appl...

Page 12: ...or quality engineer 3 4 Reflow Soldering For PCB assembly of QFP components the widely used method of reflow soldering in a forced convection oven is recommended Soldering in a nitrogen atmosphere ca...

Page 13: ...urface This shape will be frozen during cooling and therefore will result in a higher stand off on the bottom side after the reflow process Heavy vibrations in a reflow oven may cause devices to drop...

Page 14: ...lux is recommended whose residues usually do not have to be removed after the soldering process In case the solder joints have to be cleaned the cleaning method e g ultrasonic spray or vapor cleaning...

Page 15: ...ause the plating does not melt together with the solder during reflow For engineering tasks cross sectioning can offer detailed information about the solder joint quality Due to its destructive charac...

Page 16: ...t the solder paste and the reflow profile For thermal evaluations the entire thermal path must be considered as well as all boundary conditions such as the application environment or the electrical us...

Page 17: ...ior to rework might be necessary A proper drying procedure for SMD packages is described in the international J STD 033 standard 5 Please also refer to the recommendations of your PCB manufacturer and...

Page 18: ...D 3 Electronic Components Industry Association Assembly and Joining Processes and JEDEC Solid State Technology Association Committee EIA IPC JEDEC J STD 002 Solderability Tests for Component Leads Ter...

Page 19: ...2 Recommendations for Board Assembly of Infineon Quad Flat Packages Revision History Revision History Page or reference Major changes since the last revision Section 6 Rework Update of sample conditio...

Page 20: ...property rights of any third party with respect to any and all information given in this application note The data contained in this document is exclusively intended for technically trained staff It i...

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