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Infineon Cypress CYBLE-212020-01, Manual

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Infineon Cypress CYBLE-212020-01 Manual Download Page 30

Document Number: 002-12597 Rev. *H 

Page 29 of 40

CYBLE-212020-01

ITX_RF, 0dBm

Radio TX current at 0 dBm excluding 

Balun loss

–

14.2

–

mA

Guaranteed by design 

simulation

ITX,-3dBm

TX current at –3-dBm setting (PA4)

–

15.5

–

mA

ITX,-6dBm

TX current at –6-dBm setting (PA3)

–

14.5

–

mA

ITX,-12dBm

TX current at –12-dBm setting (PA2)

–

13.2

–

mA

ITX,-18dBm

TX current at –18-dBm setting (PA1)

–

12.5

–

mA

Iavg_1sec, 0dBm

Average current at 1-second Bluetooth 

LE connection interval

–

17.1

–

µA

TXP: 0 dBm; ±20-ppm 

master and slave clock 

accuracy.

For empty PDU exchange

Iavg_4sec, 0dBm

Average current at 4-second Bluetooth 

LE connection interval 

–

6.1

–

µA

TXP: 0 dBm; ±20-ppm 

master and slave clock 

accuracy.

For empty PDU exchange

General RF Specifications

FREQ

RF operating frequency

2400

–

2482

MHz

CHBW

Channel spacing

–

2

–

MHz

DR

On-air data rate

–

1000

–

kbps

IDLE2TX

Bluetooth LE.IDLE to Bluetooth LE. TX 

transition time

–

120

140

µs

IDLE2RX

Bluetooth LE.IDLE to Bluetooth LE. RX 

transition time

–

75

120

µs

RSSI Specifications

RSSI, ACC

RSSI accuracy

–

±5

–

dB

RSSI, RES

RSSI resolution

–

1

–

dB

RSSI, PER

RSSI sample period

–

6

–

µs

Table 50.  Bluetooth LE Subsystem

 (continued)

Parameter

Description

Min

Typ

Max

Units

Details/

Conditions

Summary of Contents for Cypress CYBLE-212020-01

Page 1: ...ers as part of the Infineon product portfolio Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document Future revisions will occur when appropriate and any changes will be set out on the document history page Continuity of ordering part numbers Infineon continues to support existing pa...

Page 2: ...2 bit multiply operating at up to 48 MHz Watchdog timer with dedicated internal low speed oscillator ILO Two pin SWD for programming Power Consumption TX output power 18 dbm to 3 dbm Received signal strength indicator RSSI with 1 dB resolution TX current consumption of 15 6 mA radio only 0 dbm RX current consumption of 16 4 mA radio only Low power mode support Deep Sleep 1 3 µA with watch crystal ...

Page 3: ...ery Life for BLE Applications AN85951 PSoC 4 and PSoC Analog Coprocessor Cap Sense Design Guide AN95089 PSoC 4 PRoC BLE Crystal Oscillator Selec tion and Tuning Techniques AN91445 Antenna Design and RF Layout Guidelines Technical Reference Manual TRM PRoC BLE Technical Reference Manual Knowledge Base Article KBA212838 Pin Mapping Differences Between the EZ BLE Creator Evaluation Board CYBLE 212020...

Page 4: ...ooth Low Energy Sub System BLESS hardware via the stack EZ Serial Bluetooth LE Firmware Platform The EZ Serial Firmware Platform provides a simple way to access the most common hardware and communication features needed in Bluetooth LE applications EZ Serial implements an intuitive API protocol over the UART interface and exposes various status and control signals through the module s GPIOs making...

Page 5: ...herals 21 Serial Communication 23 Memory 24 System Resources 25 Environmental Specifications 30 Environmental Compliance 30 RF Certification 30 Safety Certification 30 Environmental Conditions 30 ESD and EMI Protection 30 Regulatory Information 31 FCC 31 ISED 32 European R TTE Declaration of Conformity 32 MIC Japan 33 KC Korea 33 Packaging 34 Ordering Information 36 Part Numbering Convention 36 Ac...

Page 6: ...e component area are maintained Designs should be held within the physical dimensions shown in the mechanical drawings in Figure 1 All dimensions are in millimeters mm Table 1 Module Design Dimensions See Figure 1 on page 6 for the mechanical reference drawing for CYBLE 212020 01 Dimension Item Specification Module dimensions Length X 14 52 0 15 mm Width Y 19 20 0 15 mm Antenna location dimensions...

Page 7: ... View View from Top Bottom View Seen from Bottom Side View Note 1 No metal should be located beneath or above the antenna area Only bare PCB material should be located beneath the antenna area For more information on recommended host PCB layout see Figure 3 Figure 4 Figure 5 and Figure 6 and Table 3 ...

Page 8: ...e far corner This placement minimizes the additional recommended keep out area stated in item 2 Refer to AN96841 for module placement best practices 2 To maximize RF performance the area immediately around the Cypress Bluetooth LE module trace antenna should contain an additional keep out area where no grounding or signal trace are contained The keep out area applies to all layers of the host boar...

Page 9: ...unless otherwise noted Pad length of 1 27 mm 0 635 mm from center of the pad on either side shown in Figure 6 is the minimum recommended host pad length The host PCB layout pattern can be completed using either Figure 4 Figure 5 or Figure 6 It is not necessary to use all figures to complete the host PCB layout pattern Figure 4 Host Layout Pattern for CYBLE 212020 01 Figure 5 Module Pad Location fr...

Page 10: ...39 11 23 15 35 442 13 7 0 39 12 50 15 35 492 13 8 0 39 13 77 15 35 542 13 9 0 39 15 04 15 35 592 13 10 0 39 16 31 15 35 642 13 11 0 39 17 58 15 35 692 13 12 2 04 18 82 80 31 740 94 13 3 31 18 82 130 31 740 94 14 4 58 18 82 180 31 740 94 15 5 85 18 82 230 31 740 94 16 7 12 18 82 280 31 740 94 17 8 39 18 82 330 31 740 94 18 9 66 18 82 380 31 740 94 19 10 93 18 82 430 31 740 94 20 12 20 18 82 480 31 ...

Page 11: ...0_MOSI SCB0_SDA TCPWM Sensor 20 P1 0 TCPWM Sensor 21 P0 4 SCB0_RX SCB0_MOSI SCB0_SDA TCPWM Sensor 22 P0 5 SCB0_TX SCB0_MISO SCB0_SCL TCPWM Sensor 23 P0 7 SCB0_CTS SCB0_SCLK TCPWM Sensor SWDCLK 24 P0 6 SCB0_RTS SCB0_SS0 TCPWM Sensor SWDIO 25 GND 6 Ground Connection 26 GND 6 Ground Connection 27 GND 6 Ground Connection 28 GND 6 Ground Connection 29 VDDR Radio Power Supply 1 9 V to 5 5 V 30 P5 0 SCB1...

Page 12: ...ns are available for any application 1 Single supply Connect VDD and VDDR to the same supply 2 Independent supply Power VDD and VDDR separately External Component Recommendation In either connection scenario it is recommended to place an external ferrite bead between the supply and the module connection The ferrite bead should be positioned as close as possible to the module pin connection Figure ...

Page 13: ...Document Number 002 12597 Rev H Page 12 of 40 CYBLE 212020 01 Figure 8 Recommended Host Schematic for an Independent Supply Option Independent Power Supply Option Seen from Bottom ...

Page 14: ...Document Number 002 12597 Rev H Page 13 of 40 CYBLE 212020 01 The CYBLE 212020 01 schematic is shown in Figure 9 Figure 9 CYBLE 212020 01 Schematic Diagram ...

Page 15: ...ign Table 6 details trace antenna used in the CYBLE 212020 01 module For more information see Table 8 Table 6 Trace Antenna Specifications Component Reference Designator Description Silicon U1 56 pin QFN PSoC 4 Bluetooth LE Crystal Y1 24 000 MHz 12PF Crystal Y2 32 768 kHz 12 5PF Item Description Frequency Range 2400 2500 MHz Peak Gain 0 5 dBi typical Average Gain 0 5 dBi typical Return Loss 10 dB ...

Page 16: ...um IGPIO_ABS Maximum current per GPIO 25 25 mA Absolute maximum IGPIO_injection GPIO injection current Maximum for VIH VDD and minimum for VIL VSS 0 5 0 5 mA Absolute maximum current injected per pin LU Pin current for latch up 200 200 mA Parameter Description Min Typ Max Units Details Conditions RFO RF output power on ANT 18 0 3 dBm Configurable via register settings RXS RF receive sensitivity on...

Page 17: ...D 1 71 V to 1 89 V Regulator Bypassed IDD19 WDT with WCO on µA T 25 C IDD20 WDT with WCO on µA T 40 C to 85 C Hibernate Mode VDD 1 8 V to 3 6 V IDD27 GPIO and reset active 150 nA T 25 C VDD 3 3 V IDD28 GPIO and reset active nA T 40 C to 85 C Hibernate Mode VDD 3 6 V to 5 5 V IDD29 GPIO and reset active nA T 25 C VDD 5 V IDD30 GPIO and reset active nA T 40 C to 85 C Stop Mode VDD 1 8 V to 3 6 V IDD...

Page 18: ... 7 V 2 0 V VIL Input voltage LOW threshold 0 3 VDD V CMOS input LVTTL input VDD 2 7 V 0 3 VDD V LVTTL input VDD 2 7 V 0 8 V VOH Output voltage HIGH level VDD 0 6 V IOH 4 mA at 3 3 V VDD Output voltage HIGH level VDD 0 5 V IOH 1 mA at 1 8 V VDD VOL Output voltage LOW level 0 6 V IOL 8 mA at 3 3 V VDD Output voltage LOW level 0 6 V IOL 4 mA at 1 8 V VDD Output voltage LOW level 0 4 V IOL 3 mA at 3 3...

Page 19: ...in Typ Max Units Details Conditions IIL Input leakage absolute value VIH VDD 10 µA 25 C VDD 0 V VIH 3 0 V VOL Output voltage LOW level 0 4 V IOL 20 mA VDD 2 9 V Table 14 OVT GPIO AC Specifications P5_0 and P5_1 Only Parameter Description Min Typ Max Units Details Conditions TRISE_OVFS Output rise time in Fast Strong mode 1 5 12 ns 25 pF load 10 90 VDD 3 3 V TFALL_OVFS Output fall time in Fast Stro...

Page 20: ... neighboring I O 8 A MONO Monotonicity Yes A_GAINERR Gain error 0 1 With external reference A_OFFSET Input offset voltage 2 mV Measured with 1 V VREF A_ISAR Current consumption 1 mA A_VINS Input voltage range single ended VSS VDDA V A_VIND Input voltage range differential VSS VDDA V A_INRES Input resistance 2 2 k A_INCAP Input capacitance 10 pF VREFSAR Trimmed internal reference to SAR 1 1 Percent...

Page 21: ...linearity VDD 1 71 V to 5 5 V 1 Msps 1 2 2 LSB VREF 1 V to VDD A_DNL Differential nonlinearity VDD 1 71 V to 3 6 V 1 Msps 1 2 LSB VREF 1 71 V to VDD A_DNL Differential nonlinearity VDD 1 71 V to 5 5 V 500 ksps 1 2 2 LSB VREF 1 V to VDD A_THD Total harmonic distortion 65 dB FIN 10 kHz CSD Block Specifications Parameter Description Min Typ Max Units Details Conditions VCSD Voltage range of operation...

Page 22: ...lock current consumption at 48 MHz 535 µA 16 bit timer Table 21 Timer AC Specifications Parameter Description Min Typ Max Units Details Conditions TTIMFREQ Operating frequency FCLK 48 MHz TCAPWINT Capture pulse width internal 2 TCLK ns TCAPWEXT Capture pulse width external 2 TCLK ns TTIMRES Timer resolution TCLK ns TTENWIDINT Enable pulse width internal 2 TCLK ns TTENWIDEXT Enable pulse width exte...

Page 23: ...XT Enable pulse width external 2 TCLK ns TCTRRESWINT Reset pulse width internal 2 TCLK ns TCTRRESWEXT Reset pulse width external 2 TCLK ns Table 24 PWM DC Specifications Parameter Description Min Typ Max Units Details Conditions IPWM1 Block current consumption at 3 MHz 42 µA 16 bit PWM IPWM2 Block current consumption at 12 MHz 130 µA 16 bit PWM IPWM3 Block current consumption at 48 MHz 535 µA 16 b...

Page 24: ...ameter Description Min Typ Max Units Details Conditions II2C1 Block current consumption at 100 kHz 50 µA II2C2 Block current consumption at 400 kHz 155 µA II2C3 Block current consumption at 1 Mbps 390 µA II2C4 I2 C enabled in Deep Sleep mode 1 4 µA Table 29 Fixed I2C AC Specifications Parameter Description Min Typ Max Units Details Conditions FI2C1 Bit rate 400 kHz Parameter Description Min Typ Ma...

Page 25: ...and program voltage 1 71 5 5 V TWS48 Number of Wait states at 32 48 MHz 2 CPU execution from flash TWS32 Number of Wait states at 16 32 MHz 1 CPU execution from flash TWS16 Number of Wait states for 0 16 MHz 0 CPU execution from flash Table 37 Flash AC Specifications Parameter Description Min Typ Max Units Details Conditions TROWWRITE 9 Row block write time erase and program 20 ms Row block 256 by...

Page 26: ...rnate 1 1 V Table 42 Voltage Monitor DC Specifications Parameter Description Min Typ Max Units Details Conditions VLVI1 LVI_A D_SEL 3 0 0000b 1 71 1 75 1 79 V VLVI2 LVI_A D_SEL 3 0 0001b 1 76 1 80 1 85 V VLVI3 LVI_A D_SEL 3 0 0010b 1 85 1 90 1 95 V VLVI4 LVI_A D_SEL 3 0 0011b 1 95 2 00 2 05 V VLVI5 LVI_A D_SEL 3 0 0100b 2 05 2 10 2 15 V VLVI6 LVI_A D_SEL 3 0 0101b 2 15 2 20 2 26 V VLVI7 LVI_A D_SE...

Page 27: ...perating current at 24 MHz 325 µA IIMO3 IMO operating current at 12 MHz 225 µA IIMO4 IMO operating current at 6 MHz 180 µA IIMO5 IMO operating current at 3 MHz 150 µA Table 46 IMO AC Specifications Parameter Description Min Typ Max Units Details Conditions FIMOTOL3 Frequency variation from 3 to 48 MHz 2 With API called calibration FIMOTOL3 IMO startup time 12 µs Table 47 ILO DC Specifications Para...

Page 28: ...B RF PHY Specification RCV LE CA 03 C CI4 Adjacent channel interference Wanted signal at 67 dBm and Interferer at FRX 3 MHz 39 dB RF PHY Specification RCV LE CA 03 C CI5 Adjacent channel interference Wanted Signal at 67 dBm and Interferer at Image frequency FIMAGE 20 dB RF PHY Specification RCV LE CA 03 C CI3 Adjacent channel interference Wanted signal at 67 dBm and Interferer at Image frequency F...

Page 29: ...Specification TRM LE CA 06 C FTX MAXDR Maximum frequency drift 50 50 kHz RF PHY Specification TRM LE CA 06 C FTX INITDR Initial frequency drift 20 20 kHz RF PHY Specification TRM LE CA 06 C FTX DR Maximum drift rate 20 20 kHz 50 µs RF PHY Specification TRM LE CA 06 C IBSE1 In band spurious emission at 2 MHz offset 20 dBm RF PHY Specification TRM LE CA 03 C IBSE2 In band spurious emission at 3 MHz ...

Page 30: ...ave clock accuracy For empty PDU exchange Iavg_4sec 0dBm Average current at 4 second Bluetooth LE connection interval 6 1 µA TXP 0 dBm 20 ppm master and slave clock accuracy For empty PDU exchange General RF Specifications FREQ RF operating frequency 2400 2482 MHz CHBW Channel spacing 2 MHz DR On air data rate 1000 kbps IDLE2TX Bluetooth LE IDLE to Bluetooth LE TX transition time 120 140 µs IDLE2R...

Page 31: ...ss Bluetooth LE module Table 51 Environmental Conditions for CYBLE 212020 01 ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference EMI A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD p...

Page 32: ...different from that to which the receiver is connected Consult the dealer or an experienced radio TV technician for help LABELING REQUIREMENTS The Original Equipment Manufacturer OEM must ensure that FCC labelling requirements are met This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as...

Page 33: ...is subject to the following two conditions 1 this device may not cause interference and 2 this device must accept any interference including interference that may cause undesired operation of the device Cet appareil est conforme à la norme sur l innovation la science et le développement économique ISED norme RSS exempte de licence L exploitation est autorisée aux deux conditions suivantes 1 l appa...

Page 34: ...d additional MIC Japan certification for the end product End product can display the certification label of the embedded module KC Korea CYBLE 212020 01 is certified for use in Korea with certificate number MSIP CRM Cyp 2011 1 제품명 모델명 특정소출력무선기기 무선데이터통신시스템용 무선기기 CYBLE 212020 01 2 인증 번호 MSIP CRM Cyp 2011 3 라이선스 소유자 Cypress Semiconductor Corporation 4 제조일자 2016 5 5 제조업체 국가명 Cypress Semiconductor Corp...

Page 35: ...orientation of the CYBLE 212020 01 in the tape as well as the direction for unreeling Figure 11 Component Orientation in Tape and Unreeling Direction Table 52 Solder Reflow Peak Temperature Module Part Number Package Maximum Peak Temperature Maximum Time at PeakTemperature No of Cycles CYBLE 212020 01 31 pad SMT 260 C 30 seconds 2 Table 53 Package Moisture Sensitivity Level MSL IPC JEDEC J STD 2 M...

Page 36: ...sions used for the CYBLE 212020 01 Figure 12 Reel Dimensions The CYBLE 212020 01 is designed to be used with pick and place equipment in an SMT manufacturing environment The center of mass for the CYBLE 212020 01 is detailed in Figure 13 Figure 13 CYBLE 212020 01 Center of Mass Seen from Top ...

Page 37: ... LCD Package Packing Certified CYBLE 212020 01 48 256 Yes 2 4 1 Msps Yes Yes 31 SMT Tape and Reel Yes Table 55 Tape and Reel Package Quantity and Minimum Order Amount Description Minimum Reel Quantity Maximum Reel Quantity Comments Reel Quantity 500 500 Ships in 500 unit reel quantities Minimum Order Quantity MOQ 500 Order Increment OI 500 U S Cypress Headquarters Address 198 Champion Court San Jo...

Page 38: ... integrated design environment KC Korea Certification MIC Ministry of Internal Affairs and Communications Japan PCB printed circuit board RX receive QDID qualification design ID SMT surface mount technology a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs TCPWM timer counter pulse width modulator PWM TUV Germany Technischer Überwachun...

Page 39: ...ctions Updated Table 4 Updated TCPWM column to add TCPWM capability on Port 2 pins Added Footnote 4 C 5554670 12 15 2016 Updated Electrical Specifications Updated SAR ADC Updated Table 18 to add Note 8 to specify under what conditions the maximum number of ADC channels can be achieved D 5767776 06 08 2017 Updated Cypress Logo and Copyright E 6006702 12 27 2017 Updated reel dimensions in Figure 10 ...

Page 40: ...d description Updated hyperlinks Updated Two Easy To Use Design Environments to Get You Started Quickly Updated PSoC Creator Integrated Design Environment IDE Updated description Completing Sunset Review Document History Page continued Document Title CYBLE 212020 01 EZ BLE Creator Module Document Number 002 12597 Revision ECN Submission Date Description of Change ...

Page 41: ...ability arising out of the application or use of any product or circuit described in this document Any information provided in this document including any sample design information or programming code is provided only for reference purposes It is the responsibility of the user of this document to properly design program and test the functionality and safety of any application made of this informat...

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