Document Number: 002-12597 Rev. *H
Page 24 of 40
CYBLE-212020-01
Memory
Table 34. Fixed SPI Master Mode AC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
T
DMO
MOSI valid after SCLK driving edge
–
–
18
ns
–
T
DSI
MISO valid before SCLK capturing edge
Full clock, late MISO sampling used
20
–
–
ns
Full clock, late MISO sampling
T
HMO
Previous MOSI data hold time
0
–
–
ns
Referred to Slave capturing edge
Table 35. Fixed SPI Slave Mode AC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
T
DMI
MOSI valid before SCLK capturing edge
40
–
–
ns
T
DSO
MISO valid after SCLK driving edge
–
–
42 + 3 ×
T
CPU
ns
T
DSO_ext
MISO Valid after SCLK driving edge in
external clock mode. V
DD
< 3.0 V
–
–
50
ns
T
HSO
Previous MISO data hold time
0
–
–
ns
T
SSELSCK
SSEL valid to first SCK valid edge
100
–
–
ns
Table 36. Flash DC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
V
PE
Erase and program voltage
1.71
–
5.5
V
–
T
WS48
Number of Wait states at 32–48 MHz
2
–
–
CPU execution from flash
T
WS32
Number of Wait states at 16–32 MHz
1
–
–
CPU execution from flash
T
WS16
Number of Wait states for 0–16 MHz
0
–
–
CPU execution from flash
Table 37. Flash AC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
T
ROWWRITE
Row (block) write time (erase and
program)
–
–
20
ms
Row (block) = 256 bytes
T
ROWERASE
Row erase time
–
–
13
ms
–
T
ROWPROGRAM
Row program time after erase
–
–
7
ms
–
T
BULKERASE
[9]
Bulk erase time (256 KB)
–
–
35
ms
–
T
DEVPROG
Total device program time
–
–
25
seconds
–
F
END
Flash endurance
100 K
–
–
cycles
–
F
RET
Flash retention. T
A
55 °C, 100 K P/E
cycles
20
–
–
years
–
F
RET2
Flash retention. T
A
85 °C, 10 K P/E
cycles
10
–
–
years
–
Note
9. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have
completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make
certain that these are not inadvertently activated.