Infineon Cypress BCM43353 Manual Download Page 93

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Document Number: 002-14949 Rev. *G

Page 92 of 113

PRELIMINARY

CYW43353

17. System Power Consumption

Note:

Unless otherwise stated, these values apply for the conditions specified in

Table 26, “Recommended Operating Conditions and

DC Characteristics,”

17.1 WLAN Current Consumption

Table 42

shows the typical, total current consumed by the CYW43353. To calculate total-solution current consumption for designs

using external PAs, LNAs, and/or FEMs, add the current consumption of the external devices to the numbers in

Table 42

All values in

Table 42

are with the Bluetooth core in reset (that is, with Bluetooth off).

Table 42. Typical WLAN Current Consumption (CYW43353 Current Only)

Mode

Bandwidth

(MHz)

Band

(GHz)

VBAT = 3.6V, VDDIO = 1.8V, T

25°C

Vbat, mA

Vio

, μA

Sleep Modes

OFF

–

0.005

SLEEP

–

0.005

150

IEEE Power Save, DTIM 1

–

2.4

0.850

150

IEEE Power Save, DTIM 3

–

2.4

350

150

IEEE Power Save, DTIM 1

–

0.550

150

IEEE Power Save, DTIM 3

–

0.300

150

Active Modes

Receive

5,6

MCS8 (SGI)

2.4

CRS

2.4

Receive

5,6

MCS7 (SGI)

CRS

Receive

5,6

MCS7 (SGI)

79.5

CRS

Receive

5,6

MCS9 (SGI)

110

CRS

103

Summary of Contents for Cypress BCM43353

Page 1: ...ers as part of the Infineon product portfolio Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document Future revisions will occur when appropriate and any changes will be set out on the document history page Continuity of ordering part numbers Infineon continues to support existing pa...

Page 2: ...YW43353 brings the latest mobile connectivity technology to automotive infotainment telematics rear seat entertainment and industrial applications Offering automotive Grade 3 40C to 85C temperature performance the CYW43353 is tested to AECQ100 environmental stress guidelines and manufactured in ISO9001 and TS16949 certified facilities The CYW43353 implements highly sophisticated enhanced collabora...

Page 3: ...nd 1 bit and gSPI 48 MHz host interfaces Backward compatible with SDIO v2 0 host interfaces Integrated ARMCR4 processor with tightly coupled mem ory for complete WLAN subsystem functionality minimizing the need to wake up the applications processor for standard WLAN functions This allows for further minimization of power consumption while maintaining the ability to field upgrade with future featur...

Page 4: ...IP in hardware for faster data encryption and IEEE 802 11i compatibility Reference WLAN subsystem provides Cisco Compatible Extensions CCX CCX 2 0 CCX 3 0 CCX 4 0 CCX 5 0 Reference WLAN subsystem provides Wi Fi Protected Setup WPS Worldwide regulatory support Global products supported with worldwide homologated design Figure 1 Functional Block Diagram FEMor T R Switch VIO VBAT 5GHzW LANTX 5GHzW LA...

Page 5: ...nt 23 5 5 3 BBC Power Management 24 5 5 4 Wideband Speech 25 5 5 5 Packet Loss Concealment 25 5 5 6 Audio Rate Matching Algorithms 26 5 5 7 Codec Encoding 26 5 5 8 Multiple Simultaneous A2DP Audio Streams 26 5 6 Adaptive Frequency Hopping 26 5 7 Advanced Bluetooth WLAN Coexistence 26 5 8 Fast Connection Interlaced Page and Inquiry Scans 26 6 Microprocessor and Memory Unit for Bluetooth 27 6 1 RAM ...

Page 6: ...hing Regulator 87 16 2 3 3V LDO LDO3P3 88 16 3 2 5V LDO BTLDO2P5 89 16 4 CLDO 90 16 5 LNLDO 91 17 System Power Consumption 92 17 1 WLAN Current Consumption 92 17 2 Bluetooth Current Consumption 94 18 Interface Timing and AC Characteristics 95 18 1 SDIO gSPI Timing 95 18 1 1 SDIO Default Mode Timing 95 18 1 2 SDIO High Speed Mode Timing 96 18 1 3 SDIO Bus Timing Specifications in SDR Modes 97 18 1 ...

Page 7: ...EEE 802 11 a b g n ac MAC baseband radio and Bluetooth 4 1 enhanced data rate EDR It provides a small form factor solution with minimal external components to drive down cost for mass volumes and allows for platform flexibility in size form and function The following figure shows the interconnect of all the major physical blocks in the CYW43353 and their associated external interfaces which are de...

Page 8: ...T Diplexer Modem Bluetooth RF 2 4 GHz 5 GHz 802 11ac Dual Band Radio 1 x 1 802 11ac PHY DOT11MAC D11 Chip Common OTP NIC 301 AXI Backplane AXI2AHB AHB2AXI ARMCR4 TCM RAM768KB ROM640KB SDIOD AXI2APB GCI SECI UART and GCI GPIOs WLAN RAM Sharing WLAN BT Access GCI Coex I F Shared LNA Control and Other Coex I Fs VBAT WL_REG_ON BT_REG_ON BT_HOST_WAKE BT_DEV_WAKE UART PCM I2 S Other GPIOs BT PA 32 kHz E...

Page 9: ...WLAN receptions I2 S PCM for BT audio HCI high speed UART H4 H4 H5 transport support Wideband speech support 16 bits linear data MSB first left justified at 4K samples s for transparent air coding both through I2S and PCM interface Bluetooth SmartAudio technology improves voice and music quality for automotive and industrial applications Bluetooth low power inquiry and page scan Bluetooth Low Ener...

Page 10: ...ct with existing platform circuits In addition the TCXO and LPO inputs allow the use of existing automotive and industrial features to further minimize the size power and cost of the complete system The PCM interface provides multiple modes of operation to support both master and slave as well as hybrid interfacing to single or multiple external codec devices The UART interface supports hardware f...

Page 11: ... are powered down only when both BT_REG_ON and WL_REG_ON are deasserted The CLDO and LNLDO may be turned off and on based on the dynamic demands of the digital baseband The CYW43353 allows for an extremely low power consumption mode by completely shutting down the CBUCK CLDO and LNLDO regulators When in this state LPLDO1 and LPLDO2 which are low power linear regulators that are supplied by the sys...

Page 12: ...O WL RF CP Internal LNLDO 80 mA Internal VCOLDO 80 mA Internal LNLDO 80 mA XTAL LDO 30 mA 1 2V 1 2V 1 2V 1 2V 1 2V LNLDO 100 mA DFE DFLL PLL RXTX WLAN BBPLL DFLL WLAN BT CLB Top always on WL OTP WL PHY WL DIGITAL BT DIGITAL WL BT SRAMs CLDO Peak 300 mA Average 175 mA Bypass in deep sleep 1 2V 1 1V MEMLPLDO 3 mA VDDIO BTLDO2P5 Peak 70 mA Average 15 mA 2 5V Internal LNLDO 25 mA Internal LNLDO 8 mA L...

Page 13: ... the PMU sequencer to wake up the chip and transition to Active mode In Doze mode the primary power consumed is due to leakage current Deep sleep mode Most of the chip including both analog and digital domains and most of the regulators are powered off Logic states in the digital core are saved and preserved into a retention memory in the always ON domain before the digital core is pow ered off Up...

Page 14: ...eration This is done to prevent current paths or create loading on any digital signals in the system and enables the CYW43353 to be fully integrated in an embedded device and take full advantage of the lowest power savings modes When the CYW43353 is powered on from this state it is the same as a normal power up and the device does not retain any infor mation about its state from before it was powe...

Page 15: ...latest configuration and rec ommended components Figure 3 Recommended Oscillator Configuration A fractional N synthesizer in the CYW43353 generates the radio frequencies clocks and data packet timing enabling the CYW43353 to operate using a wide selection of frequency references For SDIO applications the recommended default frequency reference is a 37 4 MHz crystal The signal characteristics for t...

Page 16: ...ernal Frequency Reference2 3 Min Typ Max Min Typ Max Units Frequency 2 4 GHz and 5 GHz bands IEEE 802 11ac operation 35 37 4 38 4 37 4 MHz Frequency 5 GHz band IEEE 802 11n operation only 19 37 4 38 4 35 37 4 38 4 MHz Frequency 2 4 GHz band IEEE 802 11n operation and both bands legacy 802 11a b g operation only Ranges between 19 MHz and 38 4 MHz4 Frequency tolerance over the lifetime of the equipm...

Page 17: ...e frequency and programs itself to the correct reference frequency In order for automatic frequency detection to work correctly the CYW43353 must have a valid and stable 32 768 kHz LPO clock that meets the requirements listed in Table 3 and is present during power on reset Phase noise6 IEEE 802 11a 37 4 MHz clock at 10 kHz offset 137 dBc Hz 37 4 MHz clock at 100 kHz offset 144 dBc Hz Phase noise6 ...

Page 18: ...ed Use a precision external 32 768 kHz clock that meets the requirements listed in Table 3 Table 3 External 32 768 kHz Sleep Clock Specifications Parameter LPO Clock Units Nominal input frequency 32 768 kHz Frequency accuracy 200 ppm Duty cycle 30 70 Input signal amplitude 200 1800 mV p p Signal type Square wave or sine wave Input impedance1 1 When power is applied or switched off 100k 5 Ω pF Cloc...

Page 19: ...s 2 capability 4 1 Features Major Bluetooth features of the CYW43353 include Supports key features of upcoming Bluetooth standards Fully supports Bluetooth Core Specification version 4 1 Enhanced Data Rate EDR features Adaptive Frequency Hopping AFH Quality of Service QoS Extended Synchronous Connections eSCO Voice Connections Fast Connect interlaced page and inquiry scans Secure Simple Pairing SS...

Page 20: ...ation schemes 4 2 3 Digital Demodulator and Bit Synchronizer The digital demodulator and bit synchronizer take the low IF received signal and perform an optimal frequency tracking and bit syn chronization algorithm 4 2 4 Power Amplifier The fully integrated PA supports Class 1 or Class 2 output using a highly linearized temperature compensated design This provides greater flexibility in front end ...

Page 21: ... The CYW43353 uses an internal RF and IF loop filter 4 2 9 Calibration The CYW43353 radio transceiver features an automated calibration scheme that is fully self contained in the radio No user interac tion is required during normal operation or during manufacturing to provide the optimal performance Calibration optimizes the per formance of all the major blocks within the radio to within 2 of opti...

Page 22: ...FEC generation HEC generation CRC generation key generation data encryption and data whitening in the transmitter 5 1 Bluetooth 4 1 Features The BBC supports all Bluetooth 4 1 features with the following benefits Dual mode bluetooth Low Energy BT and BLE operation Extended Inquiry Response EIR Shortens the time to retrieve the device name specific profile and operating mode Encryption Pause Resume...

Page 23: ... as described in Part I 1 of the Specification of the Bluetooth System Version 3 0 This includes the transmitter tests normal and delayed loopback tests and reduced hopping sequence In addition to the standard Bluetooth Test Mode the CYW43353 also supports enhanced testing features to simplify RF debugging qualification and type approval testing These features include Fixed frequency carrier wave ...

Page 24: ...the power control handshake signals used with the UART interface Table 4 Power Control Pin Description Signal Mapped to Pin Type Description BT_DEV_WAKE BT_GPIO_0 I Bluetooth device wake up Signal from the host to the CYW43353 indicating that the host requires attention Asserted The Bluetooth device must wake up or remain awake Deasserted The Bluetooth device may sleep when sleep criteria are met ...

Page 25: ...0 BT_DEV_WAKE BT_UART_CTS_N CLK_REQ_OUT BT_GPIO_1 BT_HOST_WAKE BT_REG_ON BT_UART_RTS_N Host IOs configured Host IOs unconfigured BTH IOs configured BTH IOs unconfigured T4 T5 T3 T2 T1 Notes x T1 is the time for the host to settle its IOs after a reset x T2 is the time for the host to drive BT_REG_ON high after the host IOs are configured x T3 is the time for the BTH device to settle its IOs after ...

Page 26: ...YW43353 provides support for wideband speech WBS using on chip SmartAudio technology The CYW43353 can perform subband codec SBC as well as mSBC encoding and decoding of linear 16 bits at 16 kHz 256 kbps rate transferred over the PCM bus 5 5 5 Packet Loss Concealment Packet Loss Concealment PLC improves apparent audio quality for systems with marginal link performance Bluetooth messages are sent in...

Page 27: ...lications such as VoWLAN SCO and Video over WLAN High Fidelity BT Stereo Support is provided for platforms that share a single antenna between Bluetooth and WLAN The CYW43353 radio architecture allows for lossless simultaneous Bluetooth and WLAN reception for shared antenna applications This is possible only via an inte grated solution shared LNA and joint AGC algorithm It has superior performance...

Page 28: ... layer protocol stack is executed from the internal ROM memory External patches may be applied to the ROM based firmware to provide flexibility for bug fixes or feature additions These patches may be downloaded from the host to the CYW43353 through the UART transports 6 1 RAM ROM and Patch Memory The CYW43353 Bluetooth core has 192 KB of internal RAM which is mapped between general purpose scratch...

Page 29: ...ge of the bit clock The PCM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock In long frame synchronization mode the frame synchronization sig nal is again an active high pulse at the audio frame rate however the duration is three bit periods and the pulse starts coincident with the first bit of the...

Page 30: ...ram PCM_SYNC PCM_IN PCM_OUT FM right FM left FM right FM left BT SCO 1 Tx BT SCO 2 Tx BT SCO 3 Tx BT SCO 1 Rx BT SCO 2 Rx BT SCO 3 Rx 1 frame PCM_CLK 16 bits per SCO frame CLK 16 bits per frame 16 bits per frame Each SCO channel duplicates the data 6 times Each WBS frame duplicates the data 3 times per frame ...

Page 31: ...ations Short Frame Sync Master Mode Ref No Characteristics Minimum Typical Maximum Unit 1 PCM bit clock frequency 12 MHz 2 PCM bit clock LOW 41 ns 3 PCM bit clock HIGH 41 ns 4 PCM_SYNC delay 0 25 ns 5 PCM_OUT delay 0 25 ns 6 PCM_IN setup 8 ns 7 PCM_IN hold 8 ns 8 Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 0 25 ns PCM_BCLK PCM_SYNC PCM_OUT 1 2 3 4 5...

Page 32: ...Slave Mode Ref No Characteristics Minimum Typical Maximum Unit 1 PCM bit clock frequency 12 MHz 2 PCM bit clock LOW 41 ns 3 PCM bit clock HIGH 41 ns 4 PCM_SYNC setup 8 ns 5 PCM_SYNC hold 8 ns 6 PCM_OUT delay 0 25 ns 7 PCM_IN setup 8 ns 8 PCM_IN hold 8 ns 9 Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 0 25 ns PCM_BCLK PCM_SYNC PCM_OUT 1 2 3 4 5 6 PCM_...

Page 33: ...ter Mode Ref No Characteristics Minimum Typical Maximum Unit 1 PCM bit clock frequency 12 MHz 2 PCM bit clock LOW 41 ns 3 PCM bit clock HIGH 41 ns 4 PCM_SYNC delay 0 25 ns 5 PCM_OUT delay 0 25 ns 6 PCM_IN setup 8 ns 7 PCM_IN hold 8 ns 8 Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 0 25 ns PCM_BCLK PCM_SYNC PCM_OUT 1 2 3 4 5 PCM_IN 6 8 HIGH IMPEDANCE ...

Page 34: ...f No Characteristics Minimum Typical Maximum Unit 1 PCM bit clock frequency 12 MHz 2 PCM bit clock LOW 41 ns 3 PCM bit clock HIGH 41 ns 4 PCM_SYNC setup 8 ns 5 PCM_SYNC hold 8 ns 6 PCM_OUT delay 0 25 ns 7 PCM_IN setup 8 ns 8 PCM_IN hold 8 ns 9 Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 0 25 ns PCM_BCLK PCM_SYNC PCM_OUT 1 2 3 4 5 6 PCM_IN 7 9 HIGH I...

Page 35: ...d RTS signals The CYW43353 UART can perform XON XOFF flow control and includes hardware support for the Serial Line Input Protocol SLIP It can also perform wake on activity For example activity on the RX or CTS inputs can wake the chip from a sleep state Normally the UART baud rate is set by a configuration record downloaded after device reset or by automatic baud rate detection and the host does ...

Page 36: ...Ref No Characteristics Min Typ Max Unit 1 Delay time UART_CTS_N low to UART_TXD valid 1 5 Bit period 2 Setup time UART_CTS_N high before midpoint of stop bit 0 5 Bit period 3 Delay time midpoint of stop bit to UART_RTS_N high 0 5 Bit period UART_CTS_N UART_RXD UART_RTS_N 1 2 Midpoint of STOP bit UART_TXD 3 Midpoint of STOP bit ...

Page 37: ...synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising edge of I2S_SSCK The clock rate in master mode is either of the following 48 kHz x 32 bits per frame 1 536 MHz 48 kHz x 50 bits per frame 2 400 MHz The master clock is generated from the input reference clock using a N M clock divider In the slave mode any clock rate is supported to a maximum of 3 072...

Page 38: ...eriods are greater than 0 35Tr any clock that meets the requirements can be used 4 Because the delay tdtr and the maximum transmitter speed defined by Ttr are related a fast transmitter driven by a slow clock edge can result in tdtr not exceeding tRC which means thtr becomes zero or negative Therefore the transmitter has to guarantee that thtr is greater than or equal to zero so long as the clock ...

Page 39: ... 002 14949 Rev G Page 38 of 113 PRELIMINARY CYW43353 Figure 15 I2 S Receiver Timing SD and WS SCK VL 0 8V tLC 0 35T tHC 0 35 T VH 2 0V thr 0 tsr 0 2T T Clock period Tr Minimum allowed clock period for transmitter T Tr ...

Page 40: ...ion parameters may be stored in an internal One Time Programmable OTP memory which is read by the system software after device reset In addition customer specific parameters including the system vendor ID and the MAC address can be stored depending on the specific board design Customer accessible OTP memory is 502 bytes The initial state of all bits in an unprogrammed OTP device is 0 After any bit...

Page 41: ... for exchanging and managing data with other serial devices It is compatible with the industry standard 16550 UART and provides a FIFO size of 64 8 in each direction 8 6 JTAG Interface The CYW43353 supports the IEEE 1149 1 JTAG boundary scan standard for performing device package and PCB assembly testing during manufacturing In addition the JTAG interface allows Cypress to assist customers by usin...

Page 42: ... to force control of the gated clocks from within the device is also provided SDIO mode is enabled by strapping options Refer to Table 16 WLAN GPIO Functions and Strapping Options The following three functions are supported Function 0 Standard SDIO function Max BlockSize ByteCount 32B Function 1 Backplane Function to access the internal system on chip SoC address space Max BlockSize ByteCount 64B ...

Page 43: ...l SDIO mode the CYW43353 includes the option of using the simplified generic SPI gSPI interface protocol Characteristics of the gSPI mode include Supports up to 48 MHz operation Supports fixed delays for responses and data from device Supports alignment to host gSPI frames 16 or 32 bits Supports up to 2 KB frame size per transfer Supports little endian default and big endian configurations Support...

Page 44: ...YW43353 9 2 1 SPI Protocol The SPI protocol supports both 16 bit and 32 bit word operation Byte endianness is supported in both modes Figure 20 and Figure 21 show the basic write and write read commands Figure 20 gSPI Write Protocol Figure 21 gSPI Read Protocol ...

Page 45: ... for the first clock edge without relying on asynchronous delays 9 2 1 4 Read The read command always follows a separate write to set up the WLAN device for a read This command differs from the write read command in the following respects a chip selects go high between the command address and the data and b the time interval between the command address is not fixed 0 10 27 11 P acket length 11bits...

Page 46: ...Signal Timing Without Status 32 bit Big Endian C31 C30 C1 C0 D31 D30 D1 D0 Command 32 bits Write Data 16 n bits cs sclk mosi C31 C30 C0 D31 D30 D0 Command 32 bits Read Data 16 n bits miso cs sclk mosi Response Delay C31 C30 C0 D31 D30 D0 Command 32 bits Read Data 16 n bits miso cs sclk mosi Response Delay D1 C31 C30 C1 C0 D31 D30 D1 D0 Command 32 bits Write Data 16 n bits cs sclk mosi C31 C30 C1 C...

Page 47: ... is ready to receive data FIFO empty 7 Reserved 8 F2 Packet Available Packet is available ready in F2 TX FIFO 9 19 F2 Packet Length Length of packet available in F2 FIFO 20 F3 Packet Available Packet is available ready in F3 TX FIFO 21 31 F3 Packet Length Length of packet available in F3 FIFO C31 C0 D31 D1 D0 Read Data 16 n bits miso cs sclk mosi S0 S31 Status 32 bits C31 C0 D31 D1 D0 Command 32 b...

Page 48: ...for the availability of low power clock inside the device Once that is available the host must write to a PMU register to set the crystal frequency which turns on the PLL After the PLL is locked the chipActive interrupt is issued to the host This interrupt indicates the device awake ready status See Table 14 for information on gSPI registers In Table 14 the following notation is used for register ...

Page 49: ...ister 31 0 R 32 h0000 Same as status bit definitions x000C x000D F1 info register 0 R 1 F1 enabled 1 R 0 F1 ready for data transfer 13 2 R U 12 h40 F1 max packet size x000E x000F F2 info register 0 R U 1 F2 enabled 1 R 0 F2 ready for data transfer 15 2 R U 14 h800 F2 max packet size x0010 x0011 F3 info register 0 R U 1 F3 enabled 1 R 0 F3 ready for data transfer 15 2 R U 14 h800 F3 max packet size...

Page 50: ...rnal PMU Internal POR Device requests for reference clock Host Interaction Host polls F0 address 0x14 until it reads a predefined pattern Host sets wake up wlan bit and waits 8 ms the maximum time for reference clock availability After 8 ms host programs PLL registers to set crystal frequency Host downloads code Chip active interrupt is asserted after the PLL locks VBAT Notes 1 VBAT should not ris...

Page 51: ...igh throughput HT Support for power management schemes including WMM power save power save multi poll PSMP and multiphase PSMP operation Support for immediate ACK and Block ACK policies Interframe space timing support including RIFS Support for RTS CTS and CTS to self frame sequences for protecting frame exchanges Back off counters in hardware for supporting multiple priorities as specified in the...

Page 52: ...ulates all the hardware accelerators to perform the encryption and decryption and MIC computation and verification The accelerators implement the following cipher algorithms legacy WEP WPA TKIP WPA2 AES CCMP The PSM determines based on the frame type and association information the appropriate cipher algorithm to be used It supplies the keys to the hardware engines from an on chip key table The WE...

Page 53: ...ol of the PSM is capable of adopting timestamps received from beacon and probe response frames in order to maintain synchronization with the network The TSF module also generates trigger signals for events that are specified as offsets from the TSF timer such as uplink and down link transmission times used in PSMP 10 1 7 NAV The network allocation vector NAV timer module is responsible for maintai...

Page 54: ... reliability Algorithms to improve performance in presence of Bluetooth Automatic gain control scheme for blocking and non blocking application scenario for cellular applications Closed loop transmit power control Digital RF chip calibration algorithms to handle CMOS RF chip non idealities On the fly channel frequency and transmit power selection Supports per packet RX antenna diversity Available ...

Page 55: ...GHz receive path has a dedicated on chip LNA Control signals are available that can support the use of optional LNAs for each band which can increase the receive sensitivity by several dB 11 2 Transmit Path Baseband data is modulated and upconverted to the 2 4 GHz ISM or 5 GHz U NII bands respectively Linear on chip power amplifi ers are included which are capable of delivering high output powers ...

Page 56: ...O RCAL W L ADC BT ADC BT DAC W L PA W L PAD W L PGA W L TX G M ixer W L DAC W L A PA W L A PAD W L A PGA W L TX A M ixer W L TXLPF W L RXLPF W L RX A M ixer W L RX G M ixer W L A LNA11 W L A LNA12 SLNA W L G LNA12 BT LNA Load BT LNA GM BT PA BT RX M ixer BT TX Mixer BT RXLPF BT TXLPF Shared XO W L TXLPF W L DAC W L ADC W L RXLPF W L ATX W L GRX W L GTX W L ARX M UX BT TX BT RX BT ADC BT RXLPF BT D...

Page 57: ...F G BT_PCM_IN BT_PCM_CLK WL_VDDC WL_VDDC BT_UART_RXD RF_SW_CTRL_7 WL_VDDC BBPLL_AVS WRF_XTAL_GND1P2 BBPLL_AVDD1P2 G H GPIO_8 BT_PCM_SYNC CLK_REQ BT_VDDIO BT_VDDC BT_I2S_WS WRF_GPIO_OUT WRF_WL_LNLDOIN_VDD1P5 RF_SW_CTRL_6 WRF_VCO_GND WRF_XTAL_VDD1P5 WRF_XTAL_IN H J BT_HOST_WAKE BT_PCM_OUT BT_VDDC VSSC BT_I2S_CLK WRF_TSSI_A WRF_BUCK_GND1P5 WRF_MMD_GND1P2 WRF_PFD_GND1P2 WRF_CP_GND WRF_XTAL_OUT J K BT_...

Page 58: ...WRF_TSSI_A I 5 GHz TSSI input from an optional external power amplifier power detector H7 WRF_RES_EXT WRF_GPIO_OUT WRF_TSSI_G I O GPIO or 2 4 GHz TSSI input from an optional external power amplifier power detector RF Switch Control Lines F12 RF_SW_CTRL_0 O Programmable RF switch control lines The control lines are programmable via the driver and NVRAM file F11 RF_SW_CTRL_1 O E12 RF_SW_CTRL_2 O E11...

Page 59: ...L_OUT O XTAL oscillator output B4 LPO_IN I External sleep clock input 32 768 kHz H3 CLK_REQ O Reference clock request shared by BT and WLAN N2 NCF No Connect K1 NCF No Connect L1 NCF No Connect Bluetooth PCM G2 BT_PCM_CLK BT_PCMCLK I O PCM clock can be master output or slave input G1 BT_PCM_IN I PCM data input J3 BT_PCM_OUT O PCM data output H2 BT_PCM_SYNC I O PCM sync can be master output or slav...

Page 60: ...or left unconnected no connect B9 RREFHSIC I Unsupported Leave this pin unconnected no connect Integrated Voltage Regulators C2 SR_VDDBATA5V I Quiet VBAT C1 SR_VDDBATP5V I Power VBAT B2 SR_VLX O Cbuck switching regulator output Refer to Table 37 for details of the inductor and capacitor required on this output D1 LDO_VDD1P5 I LNLDO input F2 LDO_VDDBAT5V I LDO VBAT H11 WRF_XTAL_VDD1P5 WRF_XTAL_BUCK...

Page 61: ...t this pin to ground to minimize leakage C9 DVDD12HSIC HSIC_DVDD12 PWR HSIC is not supported Connect this pin to ground to minimize leakage G12 BBPLL_AVDD1P2 PWR 1 2V supply for baseband PLL Ground H10 WRF_VCO_GND1P2 WRF_VCO_GND GND VCO LOGEN ground K7 WRF_AFE_GND1P2 GND AFE ground J8 WRF_BUCK_GND1P5 GND Internal capacitor less LDO ground M7 WRF_LNA_2G_GND1P2 GND 2 GHz internal LNA ground M12 WRF_...

Page 62: ... L6 BT_IFVSS GND Bluetooth IF block ground L5 BT_PLLVSS GND Bluetooth PLL ground M3 BT_VCOVSS GND Bluetooth VCO ground M1 VSSF GND Ground M2 VSSF GND Ground L3 VSSF GND Ground K2 VSSF GND Ground G10 AVSS_BBPLL BBPLLAVSS GND Baseband PLL ground No Connect A2 A3 A4 A6 A7 A9 A10 A11 NC No connect Table 15 WLBGA Signal Descriptions Cont WLBGA Ball Signal Name Type Description ...

Page 63: ...ange the mode connect an external PU resistor to VDDIO or a PD resistor to GND using a 10 kΩ resistor or less Note Refer to the reference board schematics for more information Table 16 WLAN GPIO Functions and Strapping Options Pin Name WLBGAPin Default Function Description GPIO_7 D4 1 SDIO_SEL1 1 See Table 17 and Table 18 GPIO_8 H1 0 SDIO_PADVDDIO SDIO_CLK B11 1 CPU LESS1 SDIO_DATA_2 D10 1 SPI_SEL...

Page 64: ... as generic GPIOs The A_GPIO_X pins described below are multiplexed behind the CYW43353 s PCM and I2 S interface pins The multiplexed GPIO signals are described in Table 20 Table 19 GPIO Multiplexing Matrix Pin Name Pad Function Control Register Setting 0 1 2 3 4 5 6 7 15 BT_UART_CTS_N UART_CTS_N A_GPIO 1 BT_UART_RTS_N UART_RTS_N A_GPIO 0 BT_UART_RXD UART_RXD GPIO 5 BT_UART_TXD UART_TXD GPIO 4 BT_...

Page 65: ...2S_MWS O I2 S master word select I2S_MSCK O I2 S master clock I2S_SSCK I I2 S slave clock I2S_SSDO O I2S slave data output I2S_SWS I I2 S slave word select I2S_SSDI MSDI I I2 S slave master data input STATUS O Signals Bluetooth priority status TX_CON_FX I WLAN BT coexist Transmission confirmation permission for BT to transmit RF_ACTIVE O WLAN BT coexist Asserted logic high during local BT RX and T...

Page 66: ...n JTAG_SEL pin is high Pins WLBGA SDIO GPIO_0 WL_HOST_WAKE GPIO_1 WL_DEV_WAKE GPIO_2 TCK GCI_GPIO_1 or UART RX GPIO_3 TMS or GCI_GPIO_0 GPIO_4 TDI or SECI_IN GPIO_5 TDO or SECI_OUT GPIO_6 TRST_L or UART TX GPIO_7 Strap tied High GPIO_8 Strap tied High or Low GPIO_9 N A GPIO_10 N A GPIO_11 N A GPIO_12 N A GPIO_13 N A GPIO_14 N A GPIO_15 N A SDIO_CLK SDIO_CLK SDIO_CMD SDIO_CMD SDIO_DATA_0 SDIO_DATA_...

Page 67: ... BT_HOST_WAKE I O Y Input Output PU PD NoPull programmable Input Output PU PD NoPull programmable High Z NoPull Input PU Input PD BT_VDDIO BT_DEV_WAKE I O Y Input Output PU PD NoPull programmable Input PU PD NoPull programmable High Z NoPull Input PD Input PD BT_VDDIO BT_GPIO 2 3 4 5 I O Y Input Output PU PD NoPull programmable Input Output PU PD NoPull programmable High Z NoPull Input PD Input PD...

Page 68: ...ut Output PU PD NoPull programmable Default PD Input Output PU PD NoPull programmable Default PD High Z NoPull Input PD Input PD VDDIO WL GPIO_4 I O Y Input Output PU PD NoPull programmable Default NoPull Input Output PU PD NoPull programmable Default NoPull High Z NoPull Input NoPull Input NoPull VDDIO WL GPIO_5 I O Y Input Output PU PD NoPull programmable Default PD Input Output PU PD NoPull pro...

Page 69: ... prevent leakage due to floating pad SDIO_CLK for example 2 In the Power down state xx_REG_ON 0 High Z NoPull the pad is disabled because power is not supplied 3 Depending on whether the PCM interface is enabled and the configuration of PCM is in master or slave mode it can be either output or input 4 Depending on whether the I2S interface is enabled and the configuration of I2S is in master or sl...

Page 70: ...allowed Voltage transients as high as 5 0V for up to 250 seconds cumulative duration over the lifetime of the device are allowed VBAT 0 5 to 6 0 V DC supply voltage for digital I O VDDIO 0 5 to 3 9 V DC supply voltage for RF switch I Os VDDIO_RF 0 5 to 3 9 V DC input supply voltage for CLDO and LNLDO 0 5 to 1 575 V DC supply voltage for RF analog VDD1P2 0 5 to 1 32 V DC supply voltage for core VDD...

Page 71: ...arge per JEDEC EIA JESD22 C101 300 V Table 26 Recommended Operating Conditions and DC Characteristics Parameter Symbol Value Unit Minimum Typic al Maximum DC supply voltage for VBAT VBAT 3 01 4 82 V DC supply voltage for core VDD 1 14 1 2 1 26 V DC supply voltage for RF blocks in chip VDD1P2 1 14 1 2 1 26 V DC supply voltage for TCXO input buffer WRF_TCXO_VDD 1 62 1 8 1 98 V DC supply voltage for ...

Page 72: ...e CYW43353 is functional across this range of voltages Optimal RF performance specified in the data sheet however is guaranteed only for 3 13V VBAT 4 8V 2 The maximum continuous voltage is 4 8V Voltage transients up to 6 0V for up to 10 seconds cumulative duration over the lifetime of the device are allowed Voltage transients as high as 5 0V for up to 250 seconds cumulative duration over the lifet...

Page 73: ...ceiver RF Specifications Parameter Conditions Minimum Typical Maximum Unit Note The specifications in this table are measured at the chip port output unless otherwise specified General Frequency range 2402 2480 MHz RX sensitivity GFSK 0 1 BER 1 Mbps 93 5 dBm 4 DQPSK 0 01 BER 2 Mbps 95 5 dBm 8 DPSK 0 01 BER 3 Mbps 89 5 dBm Input IP3 16 dBm Maximum input at antenna 20 dBm RX LO Leakage 2 4 GHz band ...

Page 74: ...erformance CW 30 2000 MHz 0 1 BER 10 0 dBm 2000 2399 MHz 0 1 BER 27 dBm 2498 3000 MHz 0 1 BER 27 dBm 3000 MHz 12 75 GHz 0 1 BER 10 0 dBm Out of Band Blocking Performance Modulated Interferer GFSK 1 Mbps 2 698 716 MHz WCDMA 13 5 dBm 776 849 MHz WCDMA 13 8 dBm 824 849 MHz GSM850 13 5 dBm 824 849 MHz WCDMA 14 3 dBm 880 915 MHz E GSM 13 1 dBm 880 915 MHz WCDMA 13 1 dBm 1710 1785 MHz GSM1800 18 1 dBm 1...

Page 75: ...m 2545 2575 MHz 4 XGP Band 31 1 dBm 8DPSK 3 Mbps 2 698 716 MHz WCDMA 12 6 dBm 776 794 MHz WCDMA 12 6 dBm 824 849 MHz GSM850 12 7 dBm 824 849 MHz WCDMA 13 7 dBm 880 915 MHz E GSM 12 8 dBm 880 915 MHz WCDMA 12 6 dBm 1710 1785 MHz GSM1800 18 1 dBm 1710 1785 MHz WCDMA 17 4 dBm 1850 1910 MHz GSM1900 19 1 dBm 1850 1910 MHz WCDMA 18 6 dBm 1880 1920 MHz TD SCDMA 19 3 dBm 1920 1980 MHz WCDMA 18 9 dBm 2010 ...

Page 76: ...ions Minimum Typical Maximum Unit Note The specifications in this table are measured at the chip port output unless otherwise specified General Frequency range 2402 2480 MHz Basic rate GFSK TX power at Bluetooth1 11 0 13 0 dBm QPSK TX Power at Bluetooth1 8 0 10 0 dBm 8PSK TX Power at Bluetooth1 8 0 10 0 dBm Power control step 2 4 8 dB Note Output power is with TCA and TSSI enabled GFSK In Band Spu...

Page 77: ... 2545 2575 MHz XGP Band 140 dBm Hz 1 Output power will be 1 dB lower at temperatures between 15 C and 40 C 2 The typical number is measured at 3 MHz offset 3 The maximum value represents the value required for Bluetooth qualification as defined in the v4 1 specification 4 The spurious emissions during Idle mode are the same as specified in Table 28 5 Specified at the Bluetooth Antenna port 6 Meets...

Page 78: ... maximum deviation in payload for 99 9 of all frequency deviations 115 140 kHz Channel spacing 1 MHz Table 30 BLE RF Specifications Parameter Conditions Minimum Typical Maximum Unit Frequency range 2402 2480 MHz RX sense1 1 Dirty TX is On GFSK 0 1 BER 1 Mbps 95 5 dBm TX power2 2 BLE TX power can be increased to compensate for front end losses such as BPF diplexer switch etc The output is capped at...

Page 79: ...Characteristics Typical values apply for the following conditions VBAT 3 6V Ambient temperature 25 C Figure 31 Port Locations Showing Optional ePA and eLNA Applies to 2 4 GHz and 5 GHz Note All WLAN specifications are specified at the RF port unless otherwise specified 15 2 2 4 GHz Band General RF Specifications Table 31 2 4 GHz Band General RF Specifications Item Condition Minimum Typical Maximum...

Page 80: ...1 dBm 12 Mbps OFDM 93 2 dBm 18 Mbps OFDM 90 6 dBm 24 Mbps OFDM 87 3 dBm 36 Mbps OFDM 84 0 dBm 48 Mbps OFDM 79 3 dBm 54 Mbps OFDM 77 8 dBm RX sensitivity IEEE 802 11n 10 PER for 4096 octet PSDU a 2 Defined for default parameters 800 ns GI and non STBC 20 MHz channel spacing for all MCS rates MCS0 95 0 dBm MCS1 92 7 dBm MCS2 90 2 dBm MCS3 87 1 dBm MCS4 83 5 dBm MCS5 78 9 dBm MCS6 77 3 dBm MCS7 75 7 ...

Page 81: ...ut external filtering 6 776 794 MHz CDMA2000 24 dBm 824 849 MHz7 cdmaOne 25 dBm 824 849 MHz GSM850 15 dBm 880 915 MHz E GSM 16 dBm 1710 1785 MHz GSM1800 18 dBm 1850 1910 MHz GSM1800 19 dBm 1850 1910 MHz cdmaOne 26 dBm 1850 1910 MHz WCDMA 26 dBm 1920 1980 MHz WCDMA 28 5 dBm 2500 2570 MHz Band 7 45 dBm 2300 2400 MHz Band 40 50 dBm 2570 2620 MHz Band 38 45 dBm 2545 2575 MHz XGP Band 45 dBm In band st...

Page 82: ...S9 57 dBm 6 dB Maximum receiver gain 95 dB Gain control step 3 dB RSSI accuracy8 Range 95 dBm9 to 30 dBm 5 5 dB Range above 30 dBm 8 8 dB Return loss Zo 50Ω across the dynamic range 10 11 5 13 dB Receiver cascaded noise figure At maximum gain 4 dB 1 Derate by 1 5 dB for 40 C to 10 C and 55 C to 85 C 2 Sensitivity degradations for alternate settings in MCS modes MM 0 5 dB drop and SGI 2 dB drop 3 S...

Page 83: ...m Hz Harmonic level at 18 dBm with 100 duty cycle 4 8 5 0 GHz 2nd harmonic 7 5 dBm 1 MHz 7 2 7 5 GHz 3rd harmonic 17 5 dBm 1 MHz EVM Does Not Exceed TX power at the chip port for highest power level setting at 25 C and VBAT 3 6V with spectral mask and EVM compliance2 3 2 Derate by 1 5 dB for temperatures less than 10 C or more than 55 C or voltages less than 3 0V Derate by 3 0 dB for voltages of l...

Page 84: ...Bm 36 Mbps OFDM 83 dBm 48 Mbps OFDM 78 3 dBm 54 Mbps OFDM 76 8 dBm RX sensitivity IEEE 802 11n 10 PER for 4096 octet PSDU a Defined for default parameters 800 ns GI and non STBC 20 MHz channel spacing for all MCS rates MCS0 94 dBm MCS1 91 7 dBm MCS2 89 2 dBm MCS3 86 1 dBm MCS4 82 5 dBm MCS5 77 9 dBm MCS6 76 3 dBm MCS7 74 7 dBm RX sensitivity IEEE 802 11n 10 PER for 4096 octet PSDU a Defined for de...

Page 85: ...LDPC 10 PER for 4096 octet PSDU at WLAN RF port Defined for default parameters 800 ns GI LDPC coding and non STBC MCS7 20 MHz 76 4 dBm MCS8 20 MHz 73 7 dBm MCS7 40 MHz 73 6 dBm MCS8 40 MHz 70 6 dBm MCS9 40 MHz 69 1 dBm MCS7 80 MHz 70 5 dBm MCS8 80 MHz 67 1 dBm MCS9 80 MHz 65 0 dBm Blocking level for 1 dB RX sensitivity degradation without external filtering 2 776 794 MHz CDMA2000 21 dBm 824 849 MH...

Page 86: ... dB 12 Mbps OFDM 75 5 dBm 29 dB 18 Mbps OFDM 73 5 dBm 27 dB 24 Mbps OFDM 70 5 dBm 24 dB 36 Mbps OFDM 66 5 dBm 20 dB 48 Mbps OFDM 62 5 dBm 16 dB 54 Mbps OFDM 61 5 dBm 15 dB 65 Mbps OFDM 60 5 dBm 14 dB Maximum receiver gain 95 dB Gain control step 3 dB RSSI accuracy4 Range 95 dBm5 to 30 dBm 5 5 dB Range above 30 dBm 8 8 dB Return loss Zo 50Ω across the dynamic range 10 13 dB Receiver cascaded noise ...

Page 87: ...m Hz 2570 2620 MHz Band 38 156 5 dBm Hz 2545 2575 MHz XGP band 156 5 dBm Hz Harmonic level at 17 dBm 9 8 11 570 GHz 2nd harmonic 30 5 dBm MHz TX power at the chip port for highest power level setting at 25 C and VBAT 3 6V with spectral mask and EVM compliance2 3 2 Derate by 1 5 dB for temperatures less than 10 C or more than 55 C or voltages less than 3 0V Derate by 3 0 dB for voltages of less tha...

Page 88: ...1 MHz 100 dBm Table 37 Core Buck Switching Regulator CBUCK Specifications Specification Notes Min Typ Max Units Input supply voltage DC DC voltage range inclusive of disturbances 3 0 3 6 4 81 V PWM mode switching frequency CCM Load 100 mA VBAT 3 6V 2 8 4 5 2 MHz PWM output current 600 mA Output current limit 1400 mA Output voltage range Programmable 30 mV steps Default 1 35V 1 2 1 35 1 5 V PWM out...

Page 89: ... 10 seconds cumulative duration over the lifetime of the device are allowed Voltage transients as high as 5 0V for up to 250 seconds cumulative duration over the lifetime of the device are allowed V Output current 0 001 450 mA Nominal output voltage Vo Default 3 3V 3 3 V Dropout voltage At max load 200 mV Output voltage DC accuracy Includes line load regulation 5 5 Quiescent current No load 100 µA...

Page 90: ...g line load regulation load 0 1 mA 5 5 Dropout voltage At maximum load 200 mV Output current 0 1 70 mA Quiescent current No load 8 16 µA Maximum load at 70 mA 660 700 µA Leakage current Power down mode 1 5 5 μA Line regulation Vin from Vo 0 2V to 4 8V maximum load 3 5 mV V Load regulation Load from 1 mA to 70 mA Vin 3 6V 0 3 mV mA PSRR Vin Vo 0 2V Vo 2 5V Co 2 2 µF maximum load 100 Hz to 100 kHz 2...

Page 91: ...egulation Vin from Vo 0 15V to 1 5V maximum load 5 mV V Load regulation Load from 1 mA to 300 mA 0 02 0 05 mV mA Leakage current Power down 20 µA Bypass mode 1 3 µA PSRR 1 kHz Vin 1 35V Co 4 7 µF 20 dB Start up time of PMU VIO up and steady Time from the REG_ON rising edge to the CLDO reaching 1 2V 700 µs LDO turn on time LDO turn on time when rest of the chip is up 140 180 µs External output capa...

Page 92: ...from Vo 0 1V to 1 5V max load 5 mV V Load regulation Load from 1 mA to 150 mA 0 02 0 05 mV mA Leakage current Power down 10 µA Output noise 30 kHz 60 150 mA load Co 2 2 µF 100 kHz 60 150 mA load Co 2 2 µF 60 35 nV rt Hz nV rt Hz PSRR 1kHz Input 1 35V Co 2 2 µF Vo 1 2V 20 dB LDO turn on time LDO turn on time when rest of chip is up 140 180 µs External output capacitor Co Total ESR trace capacitor 5...

Page 93: ...f the external devices to the numbers in Table 42 All values in Table 42 are with the Bluetooth core in reset that is with Bluetooth off Table 42 Typical WLAN Current Consumption CYW43353 Current Only Mode Bandwidth MHz Band GHz VBAT 3 6V VDDIO 1 8V TA 25 C Vbat mA Vio1 μA Sleep Modes OFF2 0 005 5 SLEEP3 0 005 150 IEEE Power Save DTIM 14 2 4 0 850 150 IEEE Power Save DTIM 34 2 4 0 350 150 IEEE Pow...

Page 94: ...20 5 280 5 TX OFDM MCS7 at 18 7 dBm 40 5 340 5 TX OFDM MCS9 SGI at 16 2 dBm 40 5 270 5 TX OFDM MCS9 SGI at 15 7 dBm 80 5 270 5 1 VIO is specified with all pins idle not switching and not driving any loads 2 WL_REG_ON BT_REG_ON low 3 Idle not associated or inter beacon 4 Beacon Interval 102 4 ms Beacon duration 1 ms 1 Mbps Average current over the specified DTIM intervals 5 Measured using packet en...

Page 95: ...an 180 235 μA P and I Scan2 320 235 μA 500 ms Sniff Master 170 250 μA 500 ms Sniff Slave 120 250 μA DM1 DH1 Master 22 81 0 034 mA DM3 DH3 Master 28 06 0 044 mA DM5 DH5 Master 29 01 0 047 mA 3DH5 Master 27 09 0 100 mA SCO HV3 Master 7 9 0 123 mA HV3 Sniff Scan1 1 At maximum class 1 TX power 500 ms sniff four attempts slave P 1 28s and I 2 56s 11 38 0 180 mA BLE Scan2 2 No devices present A 1 28 sec...

Page 96: ...pical Maximum Unit SDIO CLK All values are referred to minimum VIH and maximum VIL2 2 Min Vih 0 7 VDDIO and max Vil 0 2 VDDIO Frequency Data Transfer mode fPP 0 25 MHz Frequency Identification mode fOD 0 400 kHz Clock low time tWL 10 ns Clock high time tWH 10 ns Clock rise time tTLH 10 ns Clock fall time tTHL 10 ns Inputs CMD DAT referenced to CLK Input setup time tISU 5 ns Input hold time tIH 5 n...

Page 97: ...values are referred to minimum VIH and maximum VIL2 2 Min Vih 0 7 VDDIO and max Vil 0 2 VDDIO Frequency Data Transfer Mode fPP 0 50 MHz Frequency Identification Mode fOD 0 400 kHz Clock low time tWL 7 ns Clock high time tWH 7 ns Clock rise time tTLH 3 ns Clock fall time tTHL 3 ns Inputs CMD DAT referenced to CLK Input setup time tISU 6 ns Input hold time tIH 2 ns Outputs CMD DAT referenced to CLK ...

Page 98: ... SDIO Clock Timing SDR Modes Table 46 SDIO Bus Clock Timing Parameters SDR Modes Parameter Symbol Minimum Maximum Unit Comments tCLK 40 ns SDR12 mode 20 ns SDR25 mode 10 ns SDR50 mode 4 8 ns SDR104 mode tCR tCF 0 2 tCLK ns tCR tCF 2 00 ns max 100 MHz CCARD 10 pF tCR tCF 0 96 ns max 208 MHz CCARD 10 pF Clock duty cycle 30 70 tCLK tCR SDIO_CLK tCF tCR ...

Page 99: ... Symbol Minimum Maximum Unit Comments SDR104 Mode tIS 1 4 ns CCARD 10 pF VCT 0 975V tIH 0 8 ns CCARD 5 pF VCT 0 975V SDR50 Mode tIS 3 0 ns CCARD 10 pF VCT 0 975V tIH 0 8 ns CCARD 5 pF VCT 0 975V SDR25 Mode tIS 3 0 ns CCARD 10 pF VCT 0 975V tIH 0 8 ns CCARD 5 pF VCT 0 975V SDR12 Mode tIS 3 0 ns CCARD 10 pF VCT 0 975V tIH 0 8 ns CCARD 5 pF VCT 0 975V tIS SDIO_CLK tIH CMD input DAT 3 0 input ...

Page 100: ...Modes 100 MHz to 208 MHz Table 48 SDIO Bus Output Timing Parameters SDR Modes up to 100 MHz Symbol Minimum Maximum Unit Comments tODLY 7 5 ns tCLK 10 ns CL 30 pF using driver type B for SDR50 tODLY 14 0 ns tCLK 20 ns CL 40 pF using for SDR12 SDR25 tOH 1 5 ns Hold time at the tODLY min CL 15 pF tODLY SDIO_CLK tOH CMD output DAT 3 0 output tCLK tOP SDIO_CLK CMD output DAT 3 0 output tCLK tODW ...

Page 101: ... Specifications in DDR50 Mode Figure 39 SDIO Clock Timing DDR50 Mode Table 49 SDIO Bus Output Timing Parameters SDR Modes 100 MHz to 208 MHz Symbol Minimum Maximum Unit Comments tOP 0 2 UI Card output phase ΔtOP 350 1550 ps Delay variation due to temp change after tuning tODW 0 60 UI tODW 2 88 ns 208 MHz ȴtOP 1550 ps Sampling point after tuning ȴtOP 350 ps Data valid window Data valid window Data ...

Page 102: ...tCR tCF 0 2 tCLK ns tCR tCF 4 00 ns max 50 MHz CCARD 10 pF Clock duty cycle 45 55 tISU2x SDIO_CLK DAT 3 0 input FPP tIH2x tISU2x tIH2x Invalid Invalid Invalid Invalid Data Data Data Data Data Data tODLY2x min tODLY2x min tODLY2x max tODLY2x max DAT 3 0 output In DDR50 mode DAT 3 0 lines are sampled on both edges of the clock not applicable for CMD line Available timing window for card output trans...

Page 103: ...SU 6 ns CCARD 10pF 1 Card Input hold time tIH 0 8 ns CCARD 10pF 1 Card Output CMD Output delay time tODLY 13 7 ns CCARD 30pF 1 Card Output hold time tOH 1 5 ns CCARD 15pF 1 Card Input DAT Input setup time tISU2x 3 ns CCARD 10pF 1 Card Input hold time tIH2x 0 8 ns CCARD 10pF 1 Card Output DAT Output delay time tODLY2x 7 0 ns CCARD 25pF 1 Card Output hold time tODLY2x 1 5 ns CCARD 15pF 1 Card ...

Page 104: ... limits are complied with T4 T5 2 5 ns Measured from 10 to 90 of VDDIO Input setup time T6 5 0 ns Setup time SIMO valid to SPI_CLK active edge Input hold time T7 5 0 ns Hold time SPI_CLK active edge to SIMO invalid Output setup time T8 5 0 ns Setup time SOMI valid before SPI_CLK rising Output hold time T9 5 0 ns Hold time SPI_CLK active edge to SOMI invalid CSX to clock2 2 SPI_CSx remains active f...

Page 105: ...led When this pin is low and WL_REG_ON is high the BT section is in reset Note For both the WL_REG_ON and BT_REG_ON pins there should be at least a 10 ms time delay between consecutive toggles where both signals have been driven low This is to allow time for the CBUCK regulator to discharge If this delay is not followed then there may be a VDDIO in rush current on the order of 36 mA during the nex...

Page 106: ...DDIO VDDIO should NOT be present first or be held high before VBAT is high VBAT VDDIO WL_REG_ON BT_REG_ON 90 of VH 2 Sleep cycles 32 678 kHz Sleep Clock Notes 1 VBAT should not rise 10 90 faster than 40 microseconds or slower than 10 milliseconds 2 VBAT should be up before or at the same time as VDDIO VDDIO should NOT be present first or be held high before VBAT is high 3 Ensure that BT_REG_ON is ...

Page 107: ...ON VBAT VDDIO WL_REG_ON BT_REG_ON 90 of VH 2 Sleep cycles 32 678 kHz Sleep Clock Notes 1 VBAT should not rise 10 90 faster than 40 microseconds or slower than 10 milliseconds 2 VBAT should be up before or at the same time as VDDIO VDDIO should NOT be present first or be held high before VBAT is high ...

Page 108: ... through the top bottom and sides of the package The equation for calculating the device junction temperature is TJ TT P x JT Where TJ Junction temperature at steady state condition C TT Package case top center temperature at steady state condition C P Device power dissipation Watts JT Package thermal characteristics no airflow C W 20 3 Environmental Characteristics For environmental characteristi...

Page 109: ...Document Number 002 14949 Rev G Page 108 of 113 PRELIMINARY CYW43353 21 Mechanical Information Figure 46 145 Ball WLBGA Package Mechanical Information 002 13196 Rev A ...

Page 110: ...Document Number 002 14949 Rev G Page 109 of 113 PRELIMINARY CYW43353 Figure 47 WLBGA Keep out Areas for PCB Layout Bottom View with Balls Facing Up Note No top layer metal is allowed in keep out areas ...

Page 111: ...site https com munity cypress com 23 1 References The references in this section may be used in conjunction with this document Note Cypress provides customer access to technical documentation and software through its https community cypress com and Downloads Support site see IoT Resources For Cypress documents replace the xx in the document number with the largest number available in the repositor...

Page 112: ...BGA and WLCSP Signal Descriptions on page 117 by changing BT_VDDO to BT_VDDIO and adding a note to the GPIO pin description Table 31 I O States Table 34 ESD Specifications Table 35 Recommended Operating Conditions and DC Characteristics by changing CIN to COUT Table 36 Bluetooth Receiver RF Specifications by deleting what was footnote e altering footnote b and adding footnote b to one additional p...

Page 113: ...PIO Functions and Strapping Options Table 18 Host Interface Selection WLBGA Package Table 19 GPIO Multiplexing Matrix Description of Control Signals Figure 44 WLAN ON Bluetooth OFF C 10 16 2014 43353 DS103 R Updated Cover page D 11 17 2014 43353 DS104 R Updated The state of the data sheet from Advance Data Sheet to Data Sheet Table 47 SDIO Bus Input Timing Parameters SDR Modes E 5449254 10 04 2016...

Page 114: ...liability arising out of the application or use of any product or circuit described in this document Any information provided in this document including any sample design information or programming code is provided only for reference purposes It is the responsibility of the user of this document to properly design program and test the functionality and safety of any application made of this inform...

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