Document Number: 002-14949 Rev. *G
Page 100 of 113
PRELIMINARY
CYW43353
■
Δt
OP
= +1550 ps for junction temperature of Δt
OP
= 90 degrees during operation
■
Δt
OP
= –350 ps for junction temperature of Δt
OP
= –20 degrees during operation
■
Δt
OP
= +2600 ps for junction temperature of Δt
OP
= –20 to +125 degrees during operation
Figure 38. Δt
OP
Consideration for Variable Data Window (SDR 104 Mode)
18.1.4 SDIO Bus Timing Specifications in DDR50 Mode
Figure 39. SDIO Clock Timing (DDR50 Mode)
Table 49. SDIO Bus Output Timing Parameters (SDR Modes 100 MHz to 208 MHz)
Symbol
Minimum
Maximum
Unit
Comments
t
OP
0
2
UI
Card output phase
Δt
OP
–350
+1550
ps
Delay variation due to temp change after tuning
t
ODW
0.60
–
UI
t
ODW
=2.88 ns @208 MHz
ȴ
t
OP
=
1550 ps
Sampling point after tuning
ȴ
t
OP
=
–350 ps
Data valid window
Data valid window
Data valid window
Sampling point after card junction heating
by +90°C from tuning temperature
Sampling point after card junction cooling
by –20°C from tuning temperature
t
CLK
t
CR
SDIO_CLK
t
CF
t
CR