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Document Number: 002-14949 Rev. *G
Page 30 of 113
PRELIMINARY
CYW43353
7.1.6 PCM Interface Timing
7.1.6.1. Short Frame Sync, Master Mode
Figure 9. PCM Timing Diagram (Short Frame Sync, Master Mode)
Table 5. PCM Interface Timing Specifications (Short Frame Sync, Master Mode)
Ref No.
Characteristics
Minimum
Typical
Maximum
Unit
1
PCM bit clock frequency
–
–
12
MHz
2
PCM bit clock LOW
41
–
–
ns
3
PCM bit clock HIGH
41
–
–
ns
4
PCM_SYNC delay
0
–
25
ns
5
PCM_OUT delay
0
–
25
ns
6
PCM_IN setup
8
–
–
ns
7
PCM_IN hold
8
–
–
ns
8
Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT
becoming high impedance
0
–
25
ns
PCM_BCLK
PCM_SYNC
PCM_OUT
1
2
3
4
5
PCM_IN
6
8
HIGH IMPEDANCE
7