On-Chip Peripheral Components
C513AO
User’s Manual
6-8
05.99
6.1.2 Port 0 and Port 2 used as Address/Data Bus
As shown in Figure 6-6 and in Figure 6-7 respectively, the output drivers of Port 0 and Port 2 can
be switched to an internal address or address/data bus for use in external memory accesses. In this
application they cannot be used as general purpose I/O, even if not all address lines are used
externally. The switching is done by an internal control signal dependent on the input level at the
EA pin and/or the contents of the program counter. If the ports are configured as an address/data
bus, the port latches are disconnected from the driver circuit. During this time, the P2 SFR remains
unchanged while the P0 SFR has “1”s written to it. Being an address/data bus, Port 0 uses a pullup
FET as shown in Figure 6-7. When a 16-bit address is used, Port 2 uses the additional strong
pullups p1 to emit “1”s for the entire external memory cycle instead of the weak ones (p2 and p3)
used during normal port activity.
Figure 6-7
Port 2 Circuitry
MCS02123
D
CLK
Bit
Latch
Q
Q
Control
Addr.
MUX
Internal
Pull Up
Arrangement
V
DD
Port
Pin
Int. Bus
Write to
Pin
Read
Latch
Latch
Read
=1
