CHEETAH Hardware User’s Manual
Imperx, Inc.
Rev. 6.2
6421 Congress Ave.
7/7/2015
Boca Raton, FL 33487
+1 (561) 989-0006
21 of 152
+ PAIR 6
7
unused
LVDS - In
Serial Data Receiver
- PAIR 6
20
unused
LVDS - In
Serial Data Receiver
- PAIR 7
8
- Z 0
LVDS - Out Camera Link Channel Tx
+ PAIR 7
21
+ Z 0
LVDS - Out Camera Link Channel Tx
- PAIR 8
9
- Z 1
LVDS - Out Camera Link Channel Tx
+ PAIR 8
22
+ Z 1
LVDS - Out Camera Link Channel Tx
+ PAIR 9
10
- Z 2
LVDS - Out Camera Link Channel Tx
- PAIR 9
23
+ Z 2
LVDS - Out Camera Link Channel Tx
- PAIR 10
11
-Z CLK
LVDS - Out Camera Link Clock Tx
+ PAIR 10
24
+ Z CLK
LVDS - Out Camera Link Clock Tx
+ PAIR 11
12
-
Z 3
LVDS - Out Camera Link Channel Tx
- PAIR 11
25
+Z 3
LVDS - Out Camera Link Channel Tx
Base Wire
13
Power Return Ground
Ground
Base Wire
26
12 VDC Power Power
Power Base
Table 1.3b
CLF Camera Output Connector 2 – Signal Mapping
1.5.3
Camera Link Physical Layer to Camera Link Receiver Bits
The timing diagram below describes how the Camera Link bits are transmitted over the physical
link. In the timing diagram below, X0, X1, X2 and X3 are the physical connections. Seven data
packets of four bits each are sent during each clock cycle and provide the 28 Camera Link Bits. In
the figure 1.5 below, Camera Link bits 0, 8, 19 and 27 are received over X0 to X3 in the first
transfer and bits 1, 9, 20 and 5 are received in the second transfer cycle. The timing for Y0 to Y3
and Z0 to Z3 physical connections is the same as X0 to X3.
